Mixing signal processing apparatus and mixing signal processing integrated circuit

ABSTRACT

User is allowed to designate a desired mode defining the respective numbers of channels and mixing buses, and processing for mixing input signals of the number of channels corresponding to the designated mode is performed repetitively to generate signals for the individual buses. The time of arrival of the last step in the mixing processing for the number of channels, corresponding to the designated mode, is detected to output an accumulation result obtained at the last step, and new accumulation is started with a digital audio signal inputted at a step following the last step. Digital audio signals processed by a first signal processing circuit are stored into a memory and transmitted to a second signal processing circuit via a cascade-connection. The second signal processing circuit adds the audio signal, processed for each of the steps, to audio signals input via the cascade-connection and writes added signal into the memory.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.12/056,099, filed Mar. 26, 2008 which claims priority to JapaneseApplication No. 2007-083139, filed Mar. 28, 2007, Japanese ApplicationNo. 2007-083140, filed Mar. 28, 2007, Japanese Application No.2007-083141, filed Mar. 28, 2007, and Japanese Application No.2007-083142, filed Mar. 28, 2007, the entire disclosures of which areherein incorporated by reference in their entirety for all purposes.

BACKGROUND

The present invention relates to a digital signal processing apparatusfor mixing which is suited for application to digital mixers etc. thatprocess sound or audio signals.

Heretofore, there have been known digital signal processing apparatus(DSPs) which perform various arithmetic operations on input digitalsignals. The DSP is used, for example, in an electronic musicalinstrument, to perform an effect impartment process for impartingvarious audio effects to tones (digital audio signals) and otherprocesses. Generally, the DSP includes an interface for connection withother DSPs; by connecting with a plurality of other DSPs via theinterface, an enhanced arithmetic capability can be achieved as a whole.Among examples of interfaces for interconnecting DSPs are a serial I/Oand audio bus I/O.

First, the serial I/O is explained. Each DSP includes a serial inputport and serial output port. The serial output port of a first DSP isconnected to the serial input port of a second DSP, so that audiosignals are transferred from the first DSP to the second DSP. Namely,unidirectional transfer of digital signals is permitted between suchdirectly-interconnected DSPs. In this case, one DAC period (one samplingperiod) is required for “serial conversion in the first DSP”→“signaltransfer”→“parallel conversion in the second DSP”.

Next, the audio bus I/O is explained. Each DSP includes an audio busI/O. When a plurality of DSPs are to be interconnected, the audio busI/Os of all of the DSPs are connected to bus lines of a common audiobus. Each of the DSPs transmits or transfers audio signals using framesallocated to the DSP. The “frames” are time sections allocated to theindividual DSPs when data are to be transferred in a DAC period bytime-divisional processing. The DSP at a transmitting end transfers, tothe common audio bus, signals in a frame allocated thereto, and the DSPat a receiving end receives, from the common audio bus, the transferredsignals in that frame. In this way, signals of a given DSP connected tothe common audio bus can be transferred to another DSP. In this case,one DAC period is required for “transmitting DSP”→“audio bus”→“receivingDSP”.

The DSP performing signal processing as noted above is also used inaudio signal mixing processing by a digital mixer. In a digital mixer, aquantity of arithmetic operations performed in mixer processingincreases/decreases in accordance with the number of channels to beprocessed, and thus, the arithmetic capability of just one DSP alone maysometimes be insufficient. In such a case, a plurality of DSPs areinterconnected via the above-mentioned interfaces to allow signals to betransferred bi-directionally between the DSPs so that mixer processingis performed cooperatively by the DSPs.

The mixer processing comprises two major processing: adjustmentprocessing, such as processing by an equalizer and compressor, foradjusting characteristics of audio signals; and mixing processing formixing audio signals after controlling levels of the audio signals.Whereas the adjustment processing varies in content depending on themodel type, operation mode, etc. of the processing apparatus, the mixingprocessing repeats same operations irrespective of the model type,operation mode, etc. of the processing apparatus. It is not efficient touse a programmable DSP in such monotonous repetition of the sameoperations.

Japanese Patent Application Laid-open Publication No. HEI-11-085155 andNo. 2003-255945 (hereinafter referred to as “Patent Literature 1” and“Patent Literature 2”, respectively) each disclose a prior art techniquewhere a DSP for performing ordinary or normal signal processing and aDSP for performing mixing processing are integrated into one chip,although the disclosed DSPs are indented for use in a tone generator ofan electronic musical instrument rather than in a digital mixer.

Patent Literature 1 discloses an integrated circuit in which arecollectively incorporated a tone generation section for generating tonesof a plurality of channels, a DSP section for performing the adjustmentprocessing (e.g., effect impartment) and a mixer section for performingthe mixing processing. The mixer section inputs signals of 96 channels,multiplies the input signals of the individual channels by eightdifferent coefficients, performs mixing of the results of themultiplication via 32 mixing buses and then outputs resultant mixedsignals of 32 channels. Here, the numbers of the input channels andmixing buses are fixed and non-changeable.

Patent Literature 2 too discloses an integrated circuit in which arecollectively incorporated a tone generation section for generating tonesof a plurality of channels, a DSP section for performing the adjustmentprocessing and a mixer section for performing the mixing processing. Themixer section can select, for each of the input channels, which signalshould be input and to which bus the signal should be output. The mixersection can select, per input channel, the numbers of times thecoefficient multiplication and mixing in a mixing bus should beperformed. Further, the mixer section can designate, for each of themixing buses, signals of how many channels and of which channels shouldbe input to that mixing bus. Thus, the mixer section disclosed in PatentLiterature 2 can achieve an extremely high degree of freedom.

However, the technique disclosed in Patent Literature 1, where thenumbers of the channels and mixing buses are fixed, can not flexiblymeet user's requests, such as 1) a request that the number of thechannels be increased although the number of the mixing buses may bedecreased, 2) a request that the adjustment processing per channel bemade more complicated with the number of the channels decreased and 3) arequest that the number of the mixing buses be increased. Similarinconvenience is encountered in a case where mixing processing isimplemented through operation of fixed microprograms; to meet theabove-mentioned request, it is necessary remake the microprograms.

In the case where arrangements are made to permit designation of inputand output channels per mixing channel as disclosed in Patent Literature2, there can be achieved a higher degree of freedom as a mixer, separateregisters are required for setting input and output channels per mixingchannel and settings have to be performed on all of these registers,which would complicate processing for managing the mixer section.

As regards algorithms of mixing processing performed in ordinary digitalmixers, an output point at which an audio signal is to be output from aninput channel to a mixing bus varies (e.g., by pre-fader/post-faderswitching), but an input point at which an audio signal is to be inputfrom a mixing bus to an output channel is fixed. Therefore, in order toimplement such mixing processing, it is not essential to permitdesignation of an output destination per mixing channel.

In some cases, mixing apparatus are designed which differ from eachother in the number of input channels, content of processing performedin the input channels, number of mixing buses, etc. in accordance withtheir requested specifications. However, the conventional DSPs can notmeet such various requirements. Besides, with the conventional DSPs,which audio transmission terminals are to be used for what purposes andwhich audio reception terminals are to be used for what purposes are notdecided in advance. Thus, in a case where mixing processing is performedcooperatively by a plurality of DSPs, it has been necessary to allocatecontent of the mixing processing to be implemented to the individualDSPs with audio signal transfer between the DSPs taken into account.Thus, designing of a circuit board and processing programs tends to bevery complicated.

In a case where a plurality of DSPs are to be interconnected in such amanner that desired signal transfer can be achieved using serial I/Os,the connection tends to be complicated like a puzzle, which would leadto very difficult designing. On the other hand, interconnecting aplurality of DSP in such a manner that desired signal transfer can beachieved using audio bus I/Os is not so difficult; however, using audiobuses of high general versatility in order to increase the number ofchannels is very wasteful and inefficient.

Further, in a case where a plurality of DSPs are interconnected in acascade fashion (i.e., “cascade-connected”), a signal received in agiven sampling period is mixed with outputs of the individual DSPs inthe next sampling period and then output to the next DSP in the stillnext sampling period. Therefore, a signal received in a given DAC periodcan not be output to the next DSP in the next DAC period. Namely, in thecase where a plurality of DSPs are cascade-connected so that an audiosignal is sequentially transferred between the DSPs, a time delay of alength equal to at least two sampling periods would be produced in thesignal per DSP. In recent business-use audio equipment, requestedspecifications to strictly eliminate undesired sample displacements aresometimes required, and thus, there is a need to minimize a time delayper DSP in the case where a plurality of DSPs are cascade-connected.

Generally, in the case where mixing apparatus are designed which differin the number of input channels, content of processing performed in theinput channels, number of mixing buses, etc. in accordance with theirrequested specifications, as noted above, the conventional DSPs wouldpresent the problem that they can not flexibly meet the variousrequirements by the DSPs being just simply interconnected. Particularly,the conventional DSPs can not properly meet a request for strictlyeliminating undesired sample displacements.

V Further, the conventional signal processing integrated circuits asdiscussed above contain a plurality of blocks, such as an input block,output block and signal processing block. In a case where signals are tobe transferred from one of the blocks to another, it has beenconventional to provide fixed connection wiring corresponding to atransfer path of the signals, which however tends to be veryinefficient. It is conceivable to replace such fixed connection wiringwith a block-to-block (inter-block) communicating memory, in which case,however, the communicating memory has to be a high-speed memory becauseit receives write accesses and read accesses from a plurality of blocks.In addition, a frequency band width necessary for the communicatingmemory increases as the number of the blocks, constituting theintegrated circuit, increases, which would make designing of theintegrated circuit more difficult.

SUMMARY OF THE INVENTION

In view of the foregoing, it is an object of the present invention toprovide a novel technique of a digital signal processing apparatus formixing digital audio signals which can be appropriately applied to mixerapparatus of various requested specifications, can simplify designing ofa signal-processing circuit board for a mixer apparatus employing aplurality of DSPs, and can facilitate designing of processing programsto be executed by the individual DSPs.

It is another object of the present invention to provide a noveltechnique of a digital signal processing apparatus for mixing or thelike which allows a signal to be readily transferred from one block toanother via a communicating memory in a signal-processing integratedcircuit board including a plurality of blocks, such as an input block,output block and signal processing block, which does not require amemory of a very high speed as the communicating memory, and which canfacilitate designing of the integrated circuit.

In order to accomplish the above-mentioned objects, the signalprocessing integrated circuit according to one aspect of the presentinvention allows a user to designate a desired mode that definesrespective desired numbers of channels and mixing buses, and itrepetitively performs processing for mixing input signals of the numberof channels corresponding to the designated mode to thereby generatemixed signals via the individual buses. For that purpose, the time pointof arrival of the last step in the mixing processing for the number ofchannels, corresponding to the designated mode, is detected to output anaccumulation result obtained at the last step, and new accumulation isstarted with a digital audio signal inputted at a step following thelast step.

Further, in the present invention, there are provided first and secondsignal processing sections. The first signal processing section performssignal processing on the basis of microprograms and thereby outputsdigital audio signals of the number of channels, corresponding to themode designated by the mode designation section, to the second signalprocessing section. The second signal processing section then performsmixing processing on the digital audio signals of the number of channelsa predetermined number of times equal to a quotient of (predeterminednumber of product-sum calculations) divided by (number of channels), andthereby outputs a given number of digital audio signals which is equalto the quotient. More specifically, one desired mode can be designatedfrom among at least two modes including “mode 1” in which the numbers ofchannels and mixing buses are J1 and K1, respectively, and “mode 2” inwhich the numbers of channels and mixing buses are J2 and K2,respectively, where J1×K1=J2×K2=H. Thus, the number of channels to besubjected to the signal processing and the number of mixing buses thatare used for the mixing can be set/changed in accordance with thedesignated mode.

In the present invention, the combination of the numbers of channels andbuses involved in the mixing processing to be performed by the mixingsignal processing circuit can be changed in accordance with one piece ofmode information. Unlike the prior art, it is not necessary todesignate, per product-sum calculation processing of each step, an audiosignal of which channel is to be inputted and then added to (mixed with)an audio signal of which bus. Further, because the first signalprocessing section capable of performing desired processing and thesecond signal processing section capable of performing mixing processingwhere the numbers of channels and mixing buses are changeable areconstructed as a one-chip integrated circuit, the present inventionallows the number of channels to be readily increased/decreased inaccordance with the signal processing to be performed per channel andalso allows the number of mixing buses to be readily changed inaccordance with the increase/decrease in the number of channels.Further, using a same-type integrated circuit, it is possible to designany desired one of a mixer where the signal processing amount perchannel is great (although the number of channels is small) while thenumber of mixing buses is great, and a mixer where the number ofchannels is great (the signal processing amount per channel is small)while the number of mixing buses is small. Thus, the present inventioncan be applied to mixer apparatus of various requested specificationsand can greatly facilitate designing of a signal-processing integratedcircuit board for a mixer apparatus employing a plurality of DSPs.Further, the present invention can provide a novel technique of a mixingdigital signal processing apparatus which can facilitate designing ofprocessing programs to be executed by the individual DSPs.

Further, according to the second aspect of the present invention, thereis provided a mixing signal processing apparatus includingcascade-connected first and second signal processing circuits, which ischaracterized by novel arrangements for cascade-transferring digitalaudio signals from the first signal processing circuit to the secondsignal processing circuit. The first signal processing circuit performsprocessing of a predetermined number of steps in each sampling period,and stores a plurality of resultant processed digital audio signals intoa storage section. For each of the steps, the first signal processingcircuit transmits the stored digital audio signal to the second signalprocessing circuit via a cascade output section. The second signalprocessing circuit adds a digital audio signal, processed for each ofthe steps, to the digital audio signal received from the first signalprocessing circuit via a cascade input section and then writes theresult of the addition into its storage section. The mixing signalprocessing apparatus also includes a mode designation section thatdesignates a mode defining numbers of channels and mixing buses, so thatthe aforementioned cascade transfer is performed for each of the stepsthat correspond to the number of channels corresponding to thedesignated mode.

Further, the present invention is characterized by a mixing signalprocessing integrated circuit equipped with the aforementioned cascadetransfer arrangements. Signal processing section for a mixer apparatuscan be constructed with ease by cascade-connecting a plurality of suchmixing signal processing integrated circuits.

When a digital audio signal is to be transferred from the first signalprocessing circuit to the second signal processing circuit via a cascadetransfer path, the present invention can reduce a time delay of thedigital audio signal processed by the second signal processing relativeto the digital audio signal transferred by the first signal processingcircuit to a length equal to one sampling period; with the prior artdiscussed above, the time delay use to be of a length equal to twosampling periods. Further, the number of digital audio signals to betransferred via the cascade transfer path (i.e., the number of mixingbuses) can be changed in accordance with a designated mode, in whichcase too the above-mentioned time delay can be of a reduced length equalto just one sampling period. Thus, the present invention can be appliedto mixer apparatus of various requested specifications and can greatlyfacilitate designing of a signal-processing integrated circuit board fora mixer apparatus employing a plurality of DSPs. Further, the presentinvention can provide a novel technique of a mixing digital signalprocessing apparatus which can facilitate designing of processingprograms to be executed by the individual DSPs.

According to the third aspect of the present invention, there isprovided a mixing apparatus comprising a plurality of cascade-connectedsignal processing integrated circuits. Each of the signal processingintegrated circuits comprises: an adjustment processing section thatthat, every sampling period, performs signal processing of apredetermined number of steps on externally-inputted digital audiosignals on the basis of microprograms and thereby outputs processeddigital audio signals; a reception section that receives, from apreceding-stage signal processing integrated circuit if any, digitalaudio signals of a predetermined number of buses; a mixing processingsection that inputs the digital audio signals of a predetermined numberof channels, corresponding to the designated mode, from the adjustmentprocessing section, performs mixing processing, via the predeterminednumber of buses corresponding to the designated mode, for mixing theinputted digital audio signals of the predetermined number of channelsfrom the adjustment processing section and the individual digital audiosignals received via the reception section, and thereby outputs mixeddigital audio signals of the predetermined number of buses; and atransmission section that transmits, to a succeeding-stage signalprocessing integrated circuit if any, the mixed digital audio signals ofthe predetermined number of buses outputted by the mixing processingsection. Here, the number of input channels in the mixing processingapparatus depends on the number of the cascade-connected signalprocessing integrated circuits.

Further, the present invention may include a mode designation sectionthat designates a mode defining respective numbers of channels andmixing buses. The reception section receives, from a preceding-stagesignal processing integrated circuit if any, digital audio signals of apredetermined number of buses corresponding to the designated mode. Themixing processing section inputs, from the adjustment processingsection, the digital audio signals of a predetermined number of channelscorresponding to the designated mode, performs mixing processing, viapredetermined number of buses corresponding to the designated mode, formixing the inputted digital audio signals of the predetermined number ofchannels from the adjustment processing section and the individualdigital audio signals received via the reception section, and therebyoutputs mixed digital audio signals of the predetermined number ofbuses. The transmission section transmits, to a succeeding-stage signalprocessing integrated circuit if any, the digital audio signals of thepredetermined number of buses outputted by the mixing processingsection. In this case, the number of input channels in the mixingprocessing apparatus depends on the mode designated by the designationsection and the number of the cascade-connected signal processingintegrated circuits.

In the mixing processing apparatus according to the present invention,signal processing integrated circuits (“MLSIs” in embodiments to belater described) corresponding to a desired number of input channels arefabricated on a printed circuit board, and a signal processing block ofthe mixing processing apparatus can be constructed by just connectingoutput terminals of the transmission section of a preceding-stage signalprocessing integrated circuit with input terminals of the receptionsection of a succeeding-stage signal processing integrated circuit in adesired pattern. Thus, the present invention can extremely simplifydesigning of the printed circuit board and signal processing to beexecuted by the individual signal processing integrated circuits andthus significantly shorten a necessary development period. Further,according to the present invention, a signal processing block of amixing processing apparatus having desired numbers of input channels andbuses can be provided by fabricating signal processing integratedcircuits, corresponding to the desired numbers of input channels andbuses, connecting output terminals of the transmission section of apreceding-stage signal processing integrated circuit with inputterminals of the reception section of a succeeding-stage signalprocessing integrated circuit in a desired pattern and setting a mode,corresponding to the desired number of buses, in each of the signalprocessing integrated circuits. Thus, the present invention canextremely simplify designing of the printed circuit board and signalprocessing to be executed by the individual signal processing integratedcircuits and thus significantly shorten a necessary development period.In this way, the present invention can be applied to mixer apparatus ofvarious requested specifications and can greatly facilitate designing ofa signal-processing integrated circuit board for a mixer apparatusemploying a plurality of DSPs. Further, the present invention canprovide a technique of a mixing digital signal processing apparatuswhich can facilitate designing of processing programs to be executed bythe individual DSPs.

According to the fourth aspect of the present invention, there isprovided a signal processing integrated circuit, which comprises: aplurality of blocks including: an input block that supplies inputsignals from outside; an output block that outputs the signals, suppliedby the input block, to outside; and a signal processing block thatprocesses the supplied signals to thereby supply processed signals; anda plurality of communicating memories corresponding to a plurality oftransfer paths between the blocks, each of the communicating memoriesincluding a data-writing front-side memory (area) and a data-readingback-side memory (area), the data-writing front-side memory and thedata-reading back-side memory being used alternately every samplingperiod. At desired timing in each sampling period, any one of the blocksat a transmitting end, which intends to transfer signals to another ofthe blocks, writes the signals into the front-side memory of thecommunicating memory, having the other block as a transfer destinationthereof, of a plurality of the communicating memories having thetransmitting-end block as a transfer source thereof, and any one of theblocks at a receiving end, which intends to receive signals from anotherof the blocks, reads the signals from the back-side memory of thecommunicating memory, having the other block as a transfer sourcethereof, of the plurality of the communicating memories having thereceiving-end block as a transfer destination thereof.

Preferably, the signal processing integrated circuit includes aplurality of the signal processing blocks, and the plurality of transferpaths include a transfer path between the signal processing blocks.

In the signal processing integrated circuit of the present invention,provided with the plurality of blocks including the signal processingblock, signals can be readily transferred from one block to another viathe communicating memory. Accesses for writing into the front-sidememory and for reading out from the back-side memory of each of thecommunicating memories are limited to those by a correspondingtransfer-source (i.e., transferred-from) block and correspondingtransfer-destination (i.e., transferred-to) block, and thus, no accessfrom the other blocks is permitted. Therefore, even if the number ofsignal transfer paths is increased, the necessary frequency band of eachof the communicating memories can be lowered. Namely, there is no needfor the communicating memories to be very-fast memories, and designingof the circuits is not so difficult. Further, with the communicatingmemories used on signal transfer paths between the plurality of signalprocessing blocks, it is possible to transfer signals from one signalprocessing block to another signal processing block within the signalprocessing integrated circuit.

The following will describe embodiments of the present invention, but itshould be appreciated that the present invention is not limited to thedescribed embodiments and various modifications of the invention arepossible without departing from the basic principles. The scope of thepresent invention is therefore to be determined solely by the appendedclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

For better understanding of the objects and other features of thepresent invention, its preferred embodiments will be describedhereinbelow in greater detail with reference to the accompanyingdrawings, in which:

FIG. 1A is a block diagram showing a general setup of circuitry of adigital mixer apparatus according to an embodiment of the presentinvention, and FIG. 1B is a diagram showing relationship between modesand respective numbers of input channels and mixing buses;

FIG. 2 is a block diagram explanatory of an example functionalconstruction of mixer processing implemented by the digital mixerapparatus shown in FIG. 1A;

FIG. 3 is a block diagram showing an example functional construction ofan input channel;

FIG. 4 is a block diagram showing an example internal construction of anMLSI shown in FIG. 1A;

FIG. 5 is a time chart showing operation timing of the MLSI:

FIG. 6 is a diagram showing example constructions of front and backsides of an I/O RAM shown in FIG. 4;

FIG. 7 is a diagram showing an internal construction of an NDSP;

FIG. 8 is a diagram showing an internal construction of an MDSP;

FIG. 9 is a time chart explanatory of the mixing processing performed bythe MDSP;

FIGS. 10A and 10B are diagrams showing a detailed construction of amixing-result output timing signal generation section shown in FIG. 8;

FIG. 11 is a conceptual diagram showing flows of signals between theMLSIs;

FIG. 12 is a time chart of cascade transfer; and

FIGS. 13A-13D are diagrams showing details of bit data transferred bythe cascade transfer between the MLSIs.

DETAILED DESCRIPTION

FIG. 1A is a block diagram showing an example general setup of circuitryformed on a main board 100 of a digital mixer apparatus according to anembodiment of the present invention. The present invention concerns amixing processing circuit formed on a printed board. The mixer apparatusshown in FIG. 1A includes a central processing unit (CPU) 141, a flashmemory 142, a random access memory (RAM) 143, a timer 144, a paneldisplay 145, an operator unit 146, a communication input/output (I/O)interface 147, a signal processing section 120, and an input/output unit110. The components 141-147 and signal processing unit 120 are connectedto a bus unit 140 so that various data can be communicated among them.The bus unit 140 includes a control bus, data bus and address bus.

The signal processing unit 120 includes a word clock oscillator 121, andMLSIs 122-1-122-n and 123-1-123-3 characterizing the embodiment. TheMLSIs 122-1-122-n (“MLSI I1-MLSI In”) are each a one-chip DSP thatperforms input-side processing, such as input channel adjustmentprocessing and mixing processing performed via mixing buses. The MLSIs123-1-123-3 (“MLSI O1-MLSI O3”) are each a one-chip DSP that performsoutput-side processing, such as output channel adjustment processing.The input-side MLSIs 122-1-122-n and output-side MLSIs 123-1-123-3 areimplemented by integrated circuits of a same type. The integratedcircuits will hereinafter be referred to simply (generically) as“MLSIs”. The input/output unit 110 includes input sections 111-1-111-nthat are interfaces for inputting digital audio signals from the outsideto the respective input-side MLSIs 122-1-122-n, and output sections112-1-112-3 that are interfaces for outputting digital audio signalsfrom the respective output-side MLSIs 123-1-123-3 to the outside.

The CPU 141 is a processing device for controlling behavior of theentire mixer apparatus. The flash memory 142 is a non-volatile memoryhaving stored therein various programs to be executed by the CPU 141 andvarious data. The RAM 143 is a volatile memory that are used as a loadarea for a program to be executed by the CPU 141 and as a working areafor the CPU 141. The timer 144 is used to generate a time interruptsignal to be given to the CPU 141. The panel display 145 is provided, onan operation panel of the mixer apparatus, for displaying variousinformation. The operator unit 146 includes operator members, such asvarious switches, knobs and faders, provided on the operation panel. Thecommunication I/O interface 147 is an interface for connecting the mixerapparatus to external equipment, such as a PC (personal computer).

The word clock oscillator 121 in the signal processing unit 120generates a word clock (i.e., clock signal of a predetermined samplingfrequency) WC that functions as a reference timing signal to be usedwhen a digital audio signal is to be processed. Generally, digitalmixers are constructed to process a signal in synchronism with a wordclock given from external equipment, and so is the instant embodiment ofthe mixer apparatus. The word clock oscillator 121 includes a PLL (PhaseLocked Loop) circuit provided therein so that a word clock WC,synchronized with a word clock given from external equipment, can begenerated stably and supplied to the MLSIs 122-1-122-n and 123-1-123-3.In a case where no word clock is supplied from external equipment, theword clock oscillator 121 may generate a word clock WC by it self.Reference numeral 131 indicates a supply line for supplying the sameword clock WC to all of the MLSIs. In the following description, it isassumed that the sampling frequency is 48 kHz.

The input/output unit 110 is a circuit for inputting/outputting analogand digital audio signals. In each of the MLSIs, there are providedrespective interfaces for an A/D (Analog/Digital) converter, D/A(Digital/Analog) converter, audio bus (“A bus”) and serial bus. Thus,input/output of analog audio signals is permitted by just providing anA/D converter in each of the input sections 111-1-111-n and providing aD/A converter in each of the output sections 112-1-112-3. Audio bus I/Ois provided in each of the input sections 111-1-111-n and outputsections 112-1-112-3, and the input sections 111-1-111-n and outputsections 112-1-112-3 are connected to the corresponding MLSIs122-1-123-3 via the audio buses (“A buses”).

Each of the MLSIs includes a plurality of digital audio input terminals.The plurality of digital audio input terminals of “MLSI I1”, forexample, are connected with lines (input ports) of the input section111-1 for inputting a plurality of channels of digital audio signalsoutput from the input section 111-1; the plurality of digital audioinput terminals of the other input-side MLSIs are connected with thecorresponding input sections in a similar manner. Each of the MLSIsincludes a plurality of digital audio output terminals. The plurality ofdigital audio output terminals of “MLSI O1”, for example, are connectedwith output ports of a plurality of channels of digital audio signals ofthe output section 112-1; the plurality of digital audio outputterminals of the other output-side MLSIs are connected with thecorresponding output sections in a similar manner. The followingparagraphs outline functions of the MLSIs.

Each of the MLSIs contains therein a DSP (NDSP) for ordinary processingand a DSP (MDSP) for mixing processing. The NDSP performs arithmeticprocessing of microprograms of 3,072 steps in one sampling period andrepeats such arithmetic processing every sampling period. The CPU 141sets the microprograms of 3,072 steps in each of the MLSIs to cause theMLSI to perform adjustment processing on a plurality of input channelsif the MLSI is an input-side MLSI, or to perform adjustment processingon a plurality of output channels if the MLSI is an output-side MLSI.The MDSP performs product-sum calculations of 3,072 steps in onesampling period and repeats such product-sum calculations every samplingperiod. The MDSP performs the product-sum calculations by operating inaccordance with control signals generated via a hardware logic circuitwithout the microprograms being set in the MDSP. The MDSP uses the 3,072steps to perform the mixing processing for adding or mixing an audiosignal of each of the channels, adjusted by the MLSI in question, to aplurality of mixing buses (i.e., with audio signals of the plurality ofmixing buses).

Each of the MLSIs is an integrated circuit having a general versatility,which contains therein a mode register and can change the numbers ofinput channels and mixing buses, which are to be processed by the MLSI,by changing a mode value set in the mode register. FIG. 1B showsrelationship between the mode and the numbers of input channels andmixing buses in the MLSI. Let it be assumed here that a same mode is setin all of the MLSIs within the signal processing unit 120 of the mixerapparatus. In the illustrated example of FIG. 1A, a same mode is set inall of “MLSI I1”-“MLSI In” and “MLSI O1”-“MLSI O3”. If “mode 1” is setin these MLSIs, “MLSI I1”-“MLSI In” (n input-side MLSIs) can process atotal of “32 channels×n” inputs because each of the input-side MLSIs caninput audio signals of 32 channels and perform the adjustment processingon the input audio signals of 32 channels. Similarly, if “mode 2” is setin the MLSIs, “MLSI In” (n input-side MLSIs) can process a total of “64channels×n” inputs, or if “mode 3” is set in the MLSIs, “MLSI In” (ninput-side MLSIs) can process a total of “48 channels×n” inputs.

Each of the MLSIs includes a cascade input terminal and cascade outputterminal. In the illustrated example of FIG. 1A, cascade connection ismade up to the last-stage MLSI (“MLSI O3”) by the cascade outputterminal of “MLSI I1” being connected to the cascade input terminal ofnext “MLSI I2”, the cascade output terminal of “MLSI I2” being connectedto the cascade input terminal of next “MLSI I3” and so on. Arrow 132indicates cascade connection lines for cascade transmission or transferfrom “MLSI I1” to “MLSI I2”; other arrows indicate similar cascadeconnection lines between the adjoining MLSIs. Through such cascadetransfer, transfer of audio signals of the plurality of mixing buses isachieved. In the case where the currently-set mode is “mode 1”, forexample, the number of the mixing buses is 96 as seen in FIG. 1B, andthus, audio signals of the 96 mixing buses (hereinafter referred to as“mixing bus 0”-“mixing bus 95”) are sequentially transferred, throughthe MLSI-to-MLSI case transfer, on a time-divisional basis per samplingperiod.

Specific manners in which the mixing and cascade transfer are performedin the instant embodiment are as follows. (1) First, in leading “MLSII1”, the MDSP mixes audio signals of input channels, having beensubjected to the adjustment processing in “MLSI I1”, to provide a mixingresult to be mixed to (i.e., mixed with a signal of) “mixing bus 0” andthen cascade-transfers the result of the mixing of “mixing bus 0” tonext “MLSI I2” as a mixed signal of “mixing bus 0”. Then, the MDSP mixesthe audio signals of the input channels, having been subjected to theadjustment processing in “MLSI I1”, to provide a mixing result to bemixed to (i.e., mixed with a signal of) “mixing bus 1” and thencascade-transfers the mixing result of “mixing bus 1” to next “MLSI I2”as a mixed signal of “mixing bus 1”. Then, in a similar manner to theaforementioned, the MDSP sequentially transfers respective mixed audiosignals of the other mixing buses (up to “mixing bus 95”) to “MLSI I2”.“MLSI I1” repeats the cascade transfer of mixed audio signals of “mixingbus 0”-“mixing bus 95” every sampling period. (2) In next “MLSI I2”, theMDSP mixes audio signals of input channels, having been subjected to theadjustment processing in “MLSI I2”, to provide a mixing result to bemixed to (i.e., mixed with a signal of) “mixing bus 0” and thencascade-transfers the mixing result of “mixing bus 0” to next “MLSI I3”as a mixed signal of “mixing bus 0”. Then, the MDSP mixes the audiosignals of the input channels, having been subjected to the adjustmentprocessing in “MLSI I2”, to provide a mixing result to be mixed to“mixing bus 1” and then cascade-transfers the mixing result of “mixingbus 1” to next “MLSI I3” as a mixed signal of “mixing bus 1”. Then, in asimilar manner to the aforementioned, the MDSP sequentially transfersrespective mixed audio signals of the other mixing buses (up to “mixingbus 95”) to “MLSI I3”. “MLSI I2” repeats the cascade transfer of mixedaudio signals of “mixing bus 0”-“mixing bus 95” every sampling period.(3) In each of “MLSI I3”-“MLSI In−1”, operations similar to those in“MLSI I2” are performed. What are ultimately cascade-transferred fromthe last-stage input-side MLSI (i.e., “MLSI In”) to the leadingoutput-side MLSI (i.e., “MLSI O1”) are the results of mixing (mixedsignals) of the predetermined number of the mixing buses correspondingto the currently-set mode. From the foregoing, it may be understood thatthe predetermined number of the mixing buses defined by thecurrently-set mode are provided on the cascade transfer lines connectingbetween the MLSIs; thus, the individual mixing buses on the cascadetransfer lines will hereinafter be referred to as “mixing bus channels”.

Each of output-side “MLSI O1”-“MLSI O3” takes out thecascade-transferred signals of the individual mixing bus channels,performs adjustment processing on the taken-out signals in the outputchannels provided within the MLSI and then supplies output signals ofthe individual output channels to the output sections 112-1-112-3. Notethat the relationship between the mode and the number of input channelsillustrated in FIG. 1B is relationship for the “number of inputchannels” when the MLSI in question is used on the input side (i.e., asan input-side MLSI). The number of output channels when the MLSI inquestion is used on the output side is chosen arbitrarily without beingbounded by the relationship of FIG. 1B. Namely, the number of outputchannels that can be processed at 3,072 steps performed by the NDSP canbe set arbitrary. Assuming that the currently-set mode in all of theinput-side MLSIs is “mode 1” in FIG. 1A, it is appropriate that, on theoutput side too, each of the MLSIs be constructed to realize about 32output channels; thus, in the instant embodiment, signals of the 96mixing bus channels are allocated to the three output-side MLSIs, 32mixing bus channel per output-side MLSI, so that the mixed signals areoutput after having been subjected to the adjustment processing on therespective output channels.

As set forth above, each of the MLSIs in the instant embodiment is anintegrated circuit having a general versatility such that the numbers ofinput channels and mixing buses to be processed by the MLSI can bechanged by changing the mode to be set. Generally, in designing a mixerapparatus, the numbers of input channels and mixing buses are determinedin accordance with the specifications of the mixer apparatus (e.g.,scale or size of the mixer apparatus), and arrangements have to be madesuch that a signal of any desired input channel can be mixed to (i.e.,mixed with a signal of) a desired mixing bus. In each of the MLSIs inthe instant embodiment, the number of mixing buses is determined inaccordance with the mode, and mixing bus channels, over which audiosignals of that number of mixing buses flow, are set on the cascadetransfer lines. Further, in each of the input-side MLSIs, an audiosignal from any desired input channel can be mixed to any desired mixingbus channel on the cascade transfer lines so that the audio signal fromthe desired input channel is mixed with a signal of the desired mixingbus. Desired number of input channels can be secured in the entire mixerapparatus by changing the total number of input-side MLSIs, i.e. bychanging the value of “n” of “MLSI I1-MLSI In”. Therefore, with theMLSIs in the instant embodiment, it is possible to readily design amixer apparatus of a desired scale.

Further, in each of the MLSIs in the instant embodiment, the adjustmentprocessing on the input and output channels and the like are performedby the MLSI executing desired operations, as designed by a humandesigner, using microprograms (as will be later detailed in relation toFIG. 7). The mixing processing, on the other hand, is performed by theMLS executing mechanical repetitive operations using a hardware logiccircuit (as will be later detailed in relation to FIG. 8). Thus, thereis no need for the human designer to code microprograms for the mixingprocessing.

FIG. 2 is a block diagram showing an example functional construction ofthe mixer processing implemented primarily by the signal processing unit120 and input/output unit 110 of the digital mixer apparatus shown inFIG. 1A. “A input” section 201 is a section for inputting analog audiosignals received via a microphone and/or signal line and converting theinput analog audio signals into digital representation via an A/Dconverter. “D input” section 202 is a section for inputting digitalaudio signals input via any of various digital communication lines, suchas AES/EBU (trademark), ADAT (trademark) and CobraNet (trademark). The Ainput section 201 and D input section 202 are blocks implemented by theinput sections 111-1-111-n. Input channel section 204 is a block forperforming the adjustment processing on the input signals (as will belater detailed in relation to FIG. 3), and this block is implemented bythe NDSPs provided in input-side “MLSI I1”-“MLSI In”. “32ch×n” in theblock of the input channel section 204 indicates that the total numberof input channels in the entire digital mixer apparatus is “32ch×n” when“mode 1” is set in all of input-side “MLSI I1”-“MLSI In” shown in FIG.1A. Input patch section 203 is a block for connecting the individualinput ports of the A input section 201 and D input section 202 with theinput channels of the input channel section 204, and this input patchsection 203 b is implemented by the audio buses connecting the inputsections 111-1-111-n and input-side “MLSI I1”-“MLSI In” of FIG. 1A andthe audio bus I/Os.

Signals of desired input channels of the input channel section 204 areselectively output to desired mixing buses (MIX and ST (stereo) buses ofMIX and ST bus sections 206 and 205), where the signals are subjected tothe mixing processing. This mixing processing is implemented by themixing processing and cascade transfer functions of the MDSPs ofinput-side “MLSI I1”-“MLSI In” shown in FIG. 1A. The “mixing buschannels” described above in relation to FIG. 1 can be regarded ascorresponding to the MIX and ST buses 206 and 205. Because it is assumedhere that the currently-set mode is “mode 1”, a total of 96 mixing busesare provided by 92 MIX buses (“MIX 1”-“MIX92”) 206 and four ST busesconsisting of stereo-A left and right (L and R) buses and stereo-B leftand right (L and R) buses. “mixing bus 0”-“mixing bus 91” correspond to“MIX 1”-“MIX92”, respectively, and “mixing bus 92”-“mixing bus 95”correspond to stereo-A left and right buses and stereo-B left and rightbuses, respectively.

Results of the mixing by the mixing bus channels 206 and 205 are outputto a corresponding MIX output channel section 208 (92 channels) and SToutput channel section 207 (2×2 channels), where they are subjected tooutput-side adjustment processing. Output signals from these outputchannel sections 207 and 208 are delivered, via an output patch section209, to output ports of an A (analog) output section 210 and digital (D)output section 211. The A output section 210 is a block for convertingthe delivered digital audio signals into analog representation via a D/Aconverter and outputting the converted analog audio signals to theoutside. The D output section 211 is a block for outputting thedelivered digital audios signal as-is (i.e., in the digitalrepresentation) via any of various digital communication lines, such asAES/EBU (trademark), ADAT (trademark) and CobraNet (trademark). Theoutput patch section 209 is a block for connecting the channels of theoutput channel sections 207 and 208 with the output ports of the Aoutput section 210 and D output section 211. The output-side adjustmentprocessing in the output channel sections 207 and 208 is implemented byoutput-side “MLSI O1”-“MLSI O3”, and the output patch section 209 isimplemented by the audio buses connecting output-side “MLSI O1”-“MLSIO3” with the output sections 112-1-112-3 and the audio bus I/Os. The Aoutput section 210 and D output section 211 are blocks implemented bythe output sections 112-1-112-3 shown in FIG. 1A.

FIG. 3 is a block diagram showing an example functional construction ofa representative one of the channels of the input channel section 204shown in FIG. 2. As shown, the input channel 300 includes an attenuator(ATT) 301, equalizer (EQ) 302, compressor (Comp) 303, volume control(Vol) 304, channel-ON switch (CH_ON) 305, stereo-ON switch (TO_ST) 306,panning adjuster (PAN) 307, pre/post switch (PP) 308, send leveladjusters (SND_L) 309, and send-ON switches (SND_ON) 310.

The attenuator 301 performs level control at a leading end portion ofthe input channel 300. The equalizer 302 performs a frequencycharacteristic adjustment process, and the compressor 303 performs anautomatic gain adjustment process. The volume control 304 performs asignal level adjustment process. The channel-ON switch 305 is a switchfor turning on or off the signal output of the input channel 300, andthe stereo-ON switch 306 is a switch for turning on or off the signaloutput of the input channel 300 to the ST bus section 205. The panningadjuster 307 adjusts balance between left and right stereo signals. Thepre/post switch 308 is provided for, when the signal of the inputchannel 300 is to be output to one of the MIX buses 206, switchingbetween a pre-fader position for taking out the signal of the inputchannel 300 at a point preceding the volume control 1304 and apost-fader position for taking out the signal of the input channel 300at a point following the volume control 1304. The send level adjusters309 each adjust a send level at which the signal is to be sent ordelivered to any one of the individual MIX buses 206. The send-ONswitches 310 are each a switch for turning on/off delivery of the signalto any one of the individual MIX buses 206. Whereas FIG. 3 shows onlythe stereo A buses of the ST bus section 205, the stereo B buses areconstructed in a similar manner to the stereo A buses. Further, all ofthe mixing buses MIX1-MIX92 are constructed in a similar manner to thestereo buses. Therefore, an output signal of any one of the inputchannels can be mixed to any desired one of the mixing buses. Whereasonly the construction of the input channels has been described above inrelation to FIG. 3, the output channels are generally similar infunctional construction to the input channels.

Of the functional construction of the aforementioned input channel, theoperations other than the multiplication operations immediatelypreceding the mixing by the mixing buses 205 and 206, i.e. theoperations indicated at 301-305 in the figure, are implemented byexecution of microprograms by the NDSP of the MLSI. To put it the otherway around, the functional construction can be set as desired per inputchannel by changing the microprograms to be executed by the NDSP.

The multiplication operations immediately preceding the mixing by themixing buses 205 and 206 and the accumulation to the mixing buses 205and 206 are carried out by the MDSP of the MLSI. Specifically, twomemory regions for writing therein results of the input-side adjustmentprocessing (i.e., memory regions secured in “Mram1” to be laterdescribed in relation to FIG. 6 and the like) are allocated in advanceper channel (the two memory regions will be referred to as “firstaddress” and “second address”). The NDSP writes the result of theprocess by the compressor (Comp) 303 (i.e., data at the pre-faderposition) into the first address and writes the result of the process bythe channel-ON switch (CH_ON) 305 (i.e., data at the post-faderposition) into the second address. Because, as will be later detailed,the mixing processing performed by the MDSP is arranged to mix signalsread out with read addresses designated on a step-by-step basis (i.e.,step-by-step read addresses set in a read address memory 803 to be laterdescribed in relation to FIG. 8), the pre/post switch (PP) 308 isimplemented by setting the read address of each of the channels into thefirst or second address in accordance with a pre-fader/post-fadersetting, per mixing bus, of that channel. For each of the ST buses 205of the mixing buses, it is only necessary for the MDSP to read out thesignal from the second address. Further, settings of the send leveladjuster (SND_L) 309 and send-ON switch (SND_ON) 310 for each of the MIXbuses 206 and settings of the stereo-ON switch (TO_ST) 306 and panningadjuster (PAN) 307 for each of the ST buses 205 are combined withcoefficients that are to be used when the signal of the channel inquestion (i.e., predetermined coefficients set in the coefficient memory802 to be later described in relation to FIG. 8) is to be supplied ormixed to each of the mixing buses for mixing processing, and thus, theaforementioned processing is completed by the coefficient multiplicationbeing performed only once by the MDSP; namely, the coefficientmultiplication by the send level adjuster (SND_L) 309 and ON/OFF controlby the send-ON switch (SND_ON) 310, for example, can be effected by onlyone coefficient multiplication.

FIG. 4 is a block diagram showing an example internal construction of arepresentative one of the MLSIs shown in FIG. 1A. The MLSI 400 includesan operation clock generation section 401, timing signal generationsection 402, control register 410, ordinary or normal processing DSP(NDSP) 431, mixing processing DSP (MDSP) 432, cascade input section(CIN) 433, cascade output section (COUT) 434, input section (IN) 435,output section (OUT) 436 and I/O RAM 420. The control register 410includes an N register (Nreg) 411, M register (Mreg) 412, CI register(CIreg) 413, CO register (COreg) 414, I register (Ireg) 415 and Oregister (Oreg) 4116. The I/O RAM 420 includes an Nram 421, Mram 422,Cram 423 and Oram 424. The I/O RAM 420 is a storage area to be used fordata transfer between the individual processing sections 431-436 (aswill be later described in relation to FIG. 6). Particularly, datawritten in the Cram 423 is cascade-transferred, via the cascade outputsection 436, to the next (i.e., succeeding-stage) MLSI, and thus, theCram 423 is a cascade-transferring storage area. Further, data writtenin the Oram 424 is transferred, via the output section 436, to theoutput section 112-1-112-3, and thus, the Oram 424 is a data-outputtingstorage area.

Each of the above-mentioned sections or blocks of the MLSI 400 will nowbe described. The operation clock generation section 401 generates localoperation clock signals (frequency of which is, for example, 166 MHz) tobe used in the MLSI 400. The timing signal generation section 402supplies timing signals necessary for the individual blocks in the MLSI400 to operate. The individual blocks in the MLSI 400, including theNDSP 431, MDSP 432 and cascade output section (COUT) 434, operate attiming responsive to the timing signals supplied from the timing signalgeneration section 402. Note that, because each of the plurality ofMLSIs shown in FIG. 1A operates independently in response to theoperation clocks generated by the operation clock generation section 401provided in that MLSI, there may occur timing differences among theoperation clocks of the MLSIs. However, because the same word clocks WCare supplied to all of the MLSIs and the timing signal generationsection 402 in each of the MLSIs generates timing signals having beensubjected to timing adjustment such that one DAC period (one samplingperiod) starts at the timing indicated by the word clock WC, it isensured that the start timing of each DAC period coincides among theMLSIs.

As outlined in relation to FIGS. 1A and 1B, the NDSP 431 is a DSP thatperforms the adjustment processing in the input channel 204 or outputchannel 207 or 208. The Nreg 411 is a register for setting microprogramsof 3,072 steps to be executed by the NDSP 431 every sampling period andcoefficient t data to be used for each of the steps. In the case wherethe MLSI in question is used on the input side (i.e., as an input-sideMLSI), the CPU 141 sets, into the Nreg 411, the microprograms forperforming the adjustment processing in the output channel 207 or 208 ofFIG. 2 and the coefficient data. Every sampling period, the NDSP 431executes the microprograms of 3,072 steps while reading out thecoefficient data. By repetition of the execution of the microprograms,the adjustment processing is performed for a plurality of channels.Audio signal (i.e., each sample data of the audio signal) to beprocessed is read out from the Nram 421, and the resultant processedsignal is written into the Nram 421, Mram 422 or Oram 424.

As outlined above in relation to FIGS. 1A and 1B, the MDSP 432 is a DSPthat performs the mixing processing via the mixing buses (ST and MIXbuses 205 and 206) of FIG. 1. The Mreg 412 is a register for settingstep-by-step coefficient data to be used during the operation of theMDSP 432 and setting step-by-step read addresses of the Mram 422. TheMreg 412 includes a mode register for setting a mode value as explainedabove in relation to FIG. 1B. The Mreg 412 does not store microprogramsfor the mixing processing; instead, the Mreg 412 contains a controlsignal generation section that generates control signals, correspondingto the mode set in the mode register, for 3,072 steps per samplingperiod by means of a hardware logic circuit. The MDSP 432 performsproduct-sum calculation processing of 3,072 steps every sampling periodon the basis of the control signals generated by the control signalgeneration section, and, by repetition of such product-sum calculationprocessing, it performs the mixing processing in each of thepredetermined number of the mixing buses corresponding to the mode. Inthe mixing processing, the coefficient data set in the Mreg 412 areused. Each audio signals to be mixed is read out from the Mram 422, andan audio signal of each of the mixing buses, with which the read-outaudio signal is to be mixed, is input via the cascade input section(CIN) 433. Mixed signal, which is the result of the mixing processing ineach of the mixing buses, is written into the Nram 421, Cram 423 andOram 424.

In the above description of FIGS. 1A and 1B, each of the MLSIs isreferred to as “DSP” in a broad sense of the integrated circuit thatprocesses signals as a one-chip circuit, while, in the above descriptionof FIG. 4, each of the NDSP and MDSP blocks is referred to as “DSP” in anarrow sense of the block that performs arithmetic processing within theintegrated circuit.

The cascade input section (CIN) 433 is a cascade-transferred signalinput circuit that functions as an interface for inputting a signalcascade-transferred from the preceding-stage MLSI. This cascade signalinput operation is achieved in cooperation with the cascade outputsection (COUT) 434 of the preceding-stage MLSI. The CIreg 413 is aregister for setting control data that define behavior of the cascadeinput section 433. The CPU 141 sets, as necessary, such control data ofthe CIreg 413 to control the behavior of the cascade input section 433.In the cascade transfer, as explained above in relation to FIGS. 1A and1B, signals of the predetermined number of the mixing buses,corresponding to the mode (indicated by the mode register in the Mreg412), are sequentially transferred every sampling period. The cascadeinput section 433 temporarily latches the sequentially-transferredsignals of the mixing buses into a FIFO (First-In-First-Out) registerprovided in the input section 433, and then it outputs the latchedsignals to the MDSP 432 (see arrow 441) at predetermined timing. TheMDSP 432 performs product-sum calculation processing of signals of aplurality of input channels in the MLSI and thereby sequentiallygenerates signals to be mixed to the mixing buses. Thus, at the timepoint when the signal to be mixed to each of the mixing buses has beengenerated, the MDSP 432 inputs thereto the signal of the mixing bus fromthe FIFO register of the cascade input section 433; then the MDSP 432mixes the generated signal with the input signal of the mixing bus. Notethat the cascade input section 433 may write the cascade-transferredsignal (hereinafter “cascade signal”) of the mixing bus directly intothe Nram 421 or Cram 423 (see arrow 442 or 443).

The cascade output section (COUT) 434 is a cascade output circuit thatfunctions as an interface for reading out the data from the Cram 423 andoutputting the read-out data to the succeeding-stage MLSI as a cascadesignal. This cascade signal output operation is achieved in cooperationwith the cascade input section (CIN) 433 of the succeeding-stage MLSI.The COreg 414 is a register for setting control data that controlbehavior of the cascade output section 434. The CPU 141 sets, asnecessary, such control data of the COreg 414 to control the behavior ofthe cascade output section 434.

The input section (IN) 435 is an input interface circuit for inputtingaudio signals from the A/D converter, audio bus and/or serial bus. Theaudio signals input via the input section 435 are written into the Nram421, Mram 422 or Oram 424. Behavior of the input section 435 is definedby control data set into the Ireg 415 by the CPU 141. The input patchsection 203 of FIG. 2 is implemented by the input section 435. Namely,indicating which signal should be written into which address of the Nram421 is equivalent to indicating which input port should be connected,via the input patch section 203, to which input channel.

The output section (OUT) 436 is an output interface circuit that readsout data of the Oram 424 and outputs the read-out data to the D/Aconverter, audio bus and/or serial bus. Behavior of the output section436 is defined by control data set into the Oreg 416 by the CPU 141. Theoutput patch section 209 of FIG. 2 is implemented by the output section436. Namely, indicating a signal of which address of the Nram 421 shouldbe output to which output line is equivalent to indicating which outputchannel should be connected, via the output patch section 209, to whichoutput port.

FIG. 5 is a time chart showing operation timing of a representative oneof the MLSIs in the instant embodiment, where the horizontal axisrepresents the time, reference numerals 511-514 represent timing of theword clocks WC. Time length between the word clocks WC represents thesampling period. 521-523 represent time sections where the adjustmentprocessing, mixing processing and cascade transfer processing areperformed in one sampling period 501. The adjustment processing 521 andmixing processing 522 are started a predetermined time, defined by“front jitter margin 531+difference margin 532”, after the timing ofeach word clock WC. Following a rear jitter margin 533 after completionof the adjustment processing 521 and mixing processing 522, the nextwork clock WC is given. The cascade transfer processing 523 is startedearlier by the difference margin 532 than the start timing of theadjustment processing 521 and mixing processing 522. This is intended toallow a cascade signal to be input, through the cascade transfer, so asto be used in the mixing processing by the time point when a signal tobe mixed with the signals of the individual mixing buses in the mixingprocessing 522 are generated, as will be later described in detail.

In the instant embodiment, where the sampling frequency is 48 kHz, onesampling period has a time length of 20.8 μsec. Because the adjustmentprocessing 521 and mixing processing 522 each perform operations of3,072 steps per sampling period in accordance with the operation clocksof 166 MHz, the processing can be completed within a time length of 18.5μsec {i.e., 1/(166×10⁶)}×3,072=18.5×10⁻⁶ sec=18.5 μsec. Thus, theadjustment processing 521 and mixing processing 522 of 3,072 steps canbe completed within one sampling period, and margins can be providedbefore and after the adjustment processing 521 and mixing processing522.

FIG. 6 shows example constructions of front and back sides of the I/ORAM 420 shown in FIG. 4. Specifically, the I/O RAM 420 has a dualstructure comprising a front-side storage area 602 and back-side storagearea 601 that have same addresses, and switching is made between thefront- and back-side storage areas 602 and 601 every sampling cycle(i.e., the front- and back-side storage areas 602 and 601 are usedalternately every sampling cycle). The front-side storage area 602 is awrite-only area (data-writing memory), while the back-side storage area601 is a read-only area (data-reading memory). Because of the dualstructure, data reading and writing can be performed simultaneously atany addresses in the I/O RAM 420. Data being read out in a givensampling period is data that was written at least one sampling periodbefore the given sampling period.

The Nram that functions in the back-side storage area 601 as a read-onlyregion of the NDSP 431 is divided into four regions, i.e. Nram1-Nram4.In the front-side storage area 602, Nram1 is a write-only region of theNDSP 431, Nram2 is a write-only region of the MDSP 432, Nram3 is awrite-only region of the input section (IN) 435, and Nram4 is awrite-only region of the cascade input section (CIN) 433. The Mram thatfunctions in the back-side storage area 601 as a read-only region of theMDSP 432 is divided into two regions, i.e. Mram1 and Mram2. In thefront-side storage area 602, Mram1 is a write-only region of the NDSP431, and Mram2 is a write-only region of the input section (IN) 435.Cram1 in the back-side storage area 601 is a read-only region of thecascade output section (COUT) 434, while Cram1 in the front-side storagearea 602 is a write-only region of the MDSP 432 or cascade input section(CIN) 433. The Oram that functions in the back-side storage area 601 asa read-only region of the output section (OUT) 436 is divided into threeregions, i.e. Oram1, Oram2 and Oram3. In the front-side storage area602, Oram1 is a write-only region of the NDSP 431, Oram2 is a write-onlyregion of the MDSP 432, and Oram3 is a write-only region of the inputsection (IN) 435.

The NDSP 431 is capable of performing the arithmetic processing of 3,072steps per sampling period, and, at each of the steps, it can read out anaudio signal from a given address of Nram1-Nram4, performs theadjustment processing on the read-out audio signal and write theprocessed result of the adjustment processing into a given address ofNram1, Mram1 or Oram1; the read and write addresses for such purposescan be set as desired in the microprograms to be executed by the NDSP431. Writing the processed signal into Nram1 is intended to again inputdata indicative of a halfway result in the NDSP 431 to the NDSP 431, byway of Nram1, for use in the adjustment processing. Writing theprocessed result into Mram1 is intended to pass the processed result ofthe adjustment processing to the mixing process by the MDSP 432. Writingthe processed result into Oram1 is intended to output the result of theadjustment processing as-is by way of the output section (OUT) 436.

The MDSP 432, which is capable of performing the arithmetic processingof 3,072 steps every sampling period, can read out audio signals fromgiven addresses of Mram1 and Mram2, perform a product-sum calculation onthe read-out audio signals to thereby mix the audio signals. Further,the MDSP 432 can mix the mixing result, acquired at a predeterminedposition of the 3,072 steps, with a cascade signal (i.e., signal of eachof the mixing buses) input from the cascade input section (CIN) 433 asindicated by arrow 611 (corresponding to arrow 441 of FIG. 4) and writethe mixing result of the mixing bus into predetermined addresses ofNram2, Oram2 and Cram1. The read addresses of the Mram can be set asdesired via the M register (Mreg) 412 per step. Timing of the cascadesignal input from the cascade input section (CIN) 433 to the MDSP 432 isadjusted so that the mixed signal (i.e., cascade signal) of each of themixing buses at a current time point has already been output from theCIN 433 to the MDSP 432 and prepared by the time point when the signalto be mixed with the cascade signal in the mixing bus is generated bythe MDSP 432, as will be later described. Write addresses to Nram2,Oram2 and Cram1 are addresses corresponding to the individual addressesand determined mechanically. Here, “mechanically” means that theaddresses can be generated by a logic circuit on the basis of clocks ofeach step in each sampling period and the number of the steps; in thiscase, no address register is necessary for storing the addresses. Forexample, where Nram2, Oram2 and Cram1 are expressed in an “array”notation, the mixing result of “mixing bus 0” is written into Nram2[0],Oram2[0] and Cram1[0], the mixing result of “mixing bus 1” is writteninto Nram2[1], Oram2[1] and Cram1[1], and so on. Writing the mixingresults into Nram2 is intended to perform again the adjustmentprocessing on the signals of the individual mixing buses. Writing themixing results into Oram2 is intended to output the signals of theindividual mixing buses as-is by way of the output section (OUT) 436.Further, writing the mixing results into Cram1 is intended tocascade-transfer the signals of the individual mixing buses to thesucceeding-stage MLSI.

Dotted-line arrow 613 (corresponding to arrow 443 of FIG. 4) pointingfrom the cascade input section (CIN) 433 to Cram1 indicates a line forwriting the cascade signal, input via the CIN 433, as-is to Cram1 whenthe cascade-transferred signals are to be cascade-transferred directlyto the succeeding-stage MLSI. If the illustrated example of FIG. 1A isconstructed in such a manner that the output-side MLSI123-1 outputs thesignals of “mixing bus 0”-“mixing bus 31” to the output section 112-1and the output-side MLSI123-2 outputs the signals of “mixing bus32”-“mixing bus 63” to the output section 112-2, then the output-sideMLSI123-1 causes the signals of “mixing bus 32”-“mixing bus 63” to passtherethrough, without being processed thereby, so that the signals arecascade-transferred directly to the output-side MLSI123-2.

The reason why a write line is indicated by arrow 612 (corresponding toarrow 442 of FIG. 4) pointing from the cascade input section (CIN) 433to Nram4 is to indicate that, in the case where the MLSI in question isused on the output side (i.e., as an output-side MLSI), thecascade-transferred signals are passed to the NDSP 431 by way of Nram tothereby cause the NDSP 431 to perform the output-side adjustmentprocessing. At that time, write addresses to Nram4 may be mechanicallyset at addresses corresponding to the individual mixing buses of thecascade signals. If Nram4 is expressed in an array notation, forexample, the mixing result of “mixing bus 0” is written into Nram4[0],the mixing result of “mixing bus 1” is written into Nram4[1], and so on.In this case, the NDSP 431 acquires signals to be supplied to theadjustment processing of the individual output channels, by reading outfrom Nram4[0] the signal to be supplied to “output channel 0”, readingout from Nram4[1] the signal to be supplied to “output channel 1”, andso on.

The cascade output section (COUT) 434 repetitively performs theoperations of mechanically reading out the mixed signals of theindividual mixing buses from Cram1 and cascade-transferring the read-outmixed signals. In the case where the aforementioned array notationscheme is employed, the mixing results of “mixing 0”, “mixing1”, . . .are stored in Cram1[0], Cram1[1], . . . Thus, the cascade output section434 cooperates with the cascade input section (CIN) 433 of thesucceeding-stage MLSI to sequentially cascade-transfer the mixed signalsof the individual mixing buses of Cram1 at predetermined timing.

The input section (IN) 435 writes audio signals, input from the A/Dconverter, audio bus and/or serial bus, into given addresses of Nram3,Mram2 or Oram3. Write addresses for this purpose can be designated asdesired via the Ireg 415. In this manner, part of the input patchsection shown in FIG. 2 is implemented. The reason why the input audiosignals are written into Nram3 is to pass the input audio signals to theinput channel adjustment processing of the NDSP 431. The reason why theinput audio signals are written into Mram2 is to pass the input audiosignals as-is to the mixing processing of the MDSP 432. Further, thereason why the input audio signals are written into Oram3 is to outputthe input audio signals as-is by way of the output section 436.

The output section (OUT) 436 reads out and outputs audio signals storedat given addresses of Oram1-Oram3 at latch timing of output signals tothe D/A converter, audio bus and/or serial bus. Read addresses for thispurpose can be designated as desired via the Oreg 416. In this manner,part of the output patch section shown in FIG. 2 is implemented. Readingout or retrieving the signals from Oram1 is intended to output theoutput signals of the adjustment processing of the NDSP 431. Retrievingthe signals from Oram2 is intended to output as-is the signals acquiredfrom the mixing buses 205 and 206 of FIG. 2. Retrieving the signals fromOram3 is intended to pass the input signals as-is to the output patchsection 209 of FIG. 2.

In FIGS. 4 and 6, thick-line arrows, which represent writing from theindividual sections 431-436 to the front-side storage area 602, show atypical example style of usage where MLSI in question is employed as aninput-side MLSI (i.e., one of MLSIs 122-1-122-n of FIG. 1A). Namely,according to this typical example style of usage on the input side,signal processing is performed such that signals input via the inputsection (IN) 435 are passed to the NDSP 431 by way of Nram3, results ofthe input channel adjustment processing of the NDSP 431 are passed tothe MDSP 432 by way of Mram1 and results of the mixing processing of theMDSP 432 are passed to the succeeding-stage MLSI by way of Cram1 (oroutput as-is by way of Oram2). Thin-line arrows, on the other hand,represent a variation or modification of the style of usage.

FIG. 7 shows example internal constructions of the NDSP 431 and Nreg411. The NDSP 431 includes an I/O RAM 711, temporary RAM 712, PRAM 713,selectors 714, 715 and 717, multiplier 716, adder 718, internal bus 719,and external RAM access circuit 720. Whereas the I/O RAM 711 is shown asprovided within the NDSP 431, it is, in practice, a storage areaprovided outside the NDSP 431 as stated above in relation to FIGS. 4 and6; as read areas, Nram1-Nram 4 correspond to the I/O RAM 711, while, aswrite areas, Nram1, Mram1 and Oram1 correspond to the I/O RAM 711. TheNreg 411 includes a coefficient data supply section 701 equipped with aninterpolation function, coefficient memory 702, microprogram memory 703,control signal generation section 704, external RAM address memory 705,and external RAM address supply section 706.

The microprogram memory 703 is a storage area for setting microprogramswhich the CPU 141 wants the NDSP 431 to execute. As explained above inrelation to FIGS. 4 and 6, the microprograms contain addresses of theI/O RAM 711 on which signals are to be read and written. The controlsignal generation section 704 generates control signals corresponding tothe above-mentioned microprograms and supplies the generated controlsignals to various sections of the NDSP 431. On the basis of the controlsignals, the NDSP 431 repetitively performing processing of 3,072 stepsin each sampling period, to thereby perform the adjustment processingfor a plurality of channels. The number of the channels, for which theadjustment processing is to be performed, differs depending on the mode,as set forth above in FIG. 1B. Thus, in “mode 3”, for example, thenumber of steps that can be used per channel can be made relativelygreat (i.e., 128 steps can be used per channel because the adjustmentprocessing may be performed for 24 channels by allocating the 3,072steps among the 24 channels). In “mode 2”, the number of steps that canbe used per channel is made relatively small (i.e., only 48 steps can beused per channel because the adjustment processing is performed for 64channels by allocating the 3,072 steps among the 64 channels). In thecase where the number of steps that can be used per channel is great,processing of one or more given blocks can be made complicate and/orfunctions can be added to the given blocks in the adjustment processingper channel shown in FIG. 3. Conversely, in the case where the number ofsteps that can be used per channel is small, processing of one or moregiven blocks sometimes has to be made simple or omitted in theadjustment processing per channel shown in FIG. 3. Because it is notnecessarily essential to perform the same adjustment processing for allof the channels to be processed, many of the 3,072 steps may beallocated to one or more selected ones of the channels so thatcomplicated adjustment processing can be performed for the selectedchannels while the remaining steps are allocated to the other channelsso that simple adjustment processing may be performed for the otherchannels.

The CPU 141 sets coefficient data for each of the steps into thecoefficient memory 702. The supply section 701 is equipped with theinterpolation function, so that coefficient data interpolated by theinterpolation function of the supply section 701 is supplied to theselector 715. When some coefficient data set in the coefficient memory702 has been changed in value, the interpolation function suppliescoefficient data having been interpolated over time in accordance withthe coefficient value change (because the rapid value change of thecoefficient data may undesirably lead to sound noise). The external RAM721 is a delay memory to be used when a long-time-delayed signal isrequired for the processing by the NDSP 431. Addresses with which toaccess the external RAM 721 are set in the external RAM address memory705. The supply section 706 supplies a predetermined accessing controlsignal to the external RAM access circuit 720 such that the external RAMaccess circuit 720 can read and write data from and to the external RAM721.

The NDSP 431 is constructed similarly to the conventionally-known DSPs.The multiplier 716 multiplies data from the I/O RAM 711 or temporary RAM712, selected by the selector 714, by coefficient data supplied from thesupply section 701 or PRAM 713 selected by the selector 715, and thenoutputs the result of the multiplication to the adder 718. The adder 718adds data from the internal bus 719, I/O RAM 711 or temporary RAM 712,selected by the selector 715, and data from the multiplier 716, and thenoutputs a result of the addition to the internal bus 719. The externalRAM access circuit 720 is connected to the internal bus 719, so thatdata present on the internal bus 719 can be written into the externalRAM 721 or data in the external RAM 721 can be read out to the internalbus 719. Data on the internal bus 719 can be written into the I/O RAM711, temporary RAM 712 or YRAM 713, or input to the selector 717. Theaforementioned various sections are constructed to perform “pipelineprocessing” such that they can read out data from the I/O RAM 711 perstep and write resultant processed data into the I/O RAM 711 per step.The NDSP 431 performs the adjustment processing (see for example FIG. 3)for a plurality of channels by these sections operating on the basis ofthe control signals generated by the control signal generation section704 in accordance with the microprograms set in the microprogram memory703.

FIG. 8 shows internal constructions of the MDSP 432 and Mreg 412. TheMDSP 432 includes an I/O RAM 811, multiplier 812, selector 813, adder814, gate 815, adder 816, and internal bus 817. Whereas the I/O RAM 811is shown as provided within the MDSP 432, it is, in practice, a storagearea provided outside the MDSP 432 as explained above in relation toFIGS. 4 and 6; as read areas, Mram1 and Mram2 correspond to the I/O RAM811, while, as write areas, Nram2, Oram2 and Cram1 correspond to the I/ORAM 711. Mreg 412 includes a coefficient data supply section 801equipped with an interpolation function, coefficient memory 802, I/O RAMread address memory 803, read address supply section 804, mode register805, control signal generation section 806, and mixing-result outputtiming signal generation section 807.

The mode register 805 is a register for setting one of the modesexplained above in relation to FIG. 1B. The control signal generationsection 806 is a hardware logic circuit that generates control signalsfor controlling behavior of the various sections of the MDSP 432 inaccordance with the set mode and supplies the generated control signalsto the various sections. The MDSP 432 repetitively performs processingof 3,072 steps in each sampling period, to thereby perform the mixingprocessing. The mixing-result output timing signal generation section807 is provided within the control signal generation section 806.Primarily, the mixing-result output timing signal generation section 807generates timing signals for controlling timing of selection by theselector 813 and addition by the adder 816; the timing will be laterdescribed in detail in relation to FIG. 9. The coefficient memory 802 isa storage means for setting coefficient data per step. The interpolationfunction of the supply section 801 is similar to that of the supplysection 701 of FIG. 7, by which interpolated coefficient data issupplied to the multiplier 812 per step. The I/O RAM read address memory803 is a register for setting a read address per step. The supplysection 804 reads out the read address from the memory 803 per step andsupplies the read address to the I/O RAM 811.

At each of the steps, the multiplier 812 multiplies data read out fromthe I/O RAM 811 (Mram) with the address of that step, supplied by thesupply section 804, by the coefficient data of the step supplied by thesupply section 801, and it outputs the result of the multiplication tothe adder 814. The selector 813 selectively outputs a value “0” atpredetermined timing signaled by the mixing-result output timing signalgeneration section 807, but, at other timing, the selector 813selectively outputs a result of addition by the adder 814. The adder 814adds the output from the multiplier 812 and the output from the selector813, and then it outputs the result of the addition. Although notspecifically shown, there is provided an accumulator in a path extendingfrom the output of the multiplier 814 back to the input of the selector813, so that a result of addition by the adder 814 at any given step istemporarily stored into the accumulator, and the temporarily storedresult becomes an input to the selector 813 at the next step. Therefore,the addition result input to the selector 813 is the result of theaddition performed by the adder 814 at the preceding step. Atpredetermined timing signaled by the mixing-result output timing signalgeneration section 807, the adder 816 adds the output from the adder 814and cascade signal (signal of the mixing bus) given from the cascadeinput section (CIN) 433 via the gate 815, and then it writes the resultsof the addition into the I/O RAM 811 by way of the internal bus 817. Asstated above in relation to FIG. 6, this writing operation is intendedto mechanically write the mixing results of the individual mixing busesinto corresponding positions of Nram2, Oram2 and Cram1. Write addressesto be used in this writing operation are contained in advance in thecontrol signals generated in accordance with the currently-set mode. Theaforementioned various sections are constructed to perform “pipelineprocessing” such that they can read out data from the I/O RAM 811 perstep and write resultant processed data into the I/O RAM 811 per step.If the gate 815 is closed, the audio signals cascade-input from thepreceding stage are prevented from being added; thus, as the result ofthe mixing bus processing by the MLSI is output, then new cascadetransfer will start at this point. Therefore, in the case where thecircuit board shown in FIG. 1A is used, such a style of usage allowseach of MLSIs to operate as an independent mixer by dividing x (anarbitrary integral number) preceding MLSIs and y (arbitrary integralnumber) succeeding MLSIs into groups. In such a case, the (x+1)th MLSImay be assigned to perform the input-side processing with the gate 815closed, and the cascade may be divided at the (x+1)th MLSI.

Where the MLSI in question is employed as an input-side MLSI, the gate815 is always kept in opened so that the MDSP 432 can receive thecascade signal from the preceding-stage MLSI. Where the MLSI in questionis employed as an output-side MLSI, on the other hand, the MDSP 432 isnot used in the typical style of usage, and thus, the gate 815 is alwayskept closed. The “typical style of usage” on the output side is, forexample, a style where, of the signals of the mixing busescascade-transferred from the input-side MLSI, only the signal to besubjected to the adjustment processing in the output channel of the MLSIis passed from the cascade input section (CIN) 433 to the NDSP 431 viaNram4 so that the adjustment processing is performed thereon by the NDSP431—all of the signals, including the signal to be subjected to theadjustment processing in the output channel of the MLSI, are passed fromthe cascade input section 433 to the succeeding-stage output-side MLSIwithout being processed by the MDSP 432-, and the result of theadjustment processing of the output channel by the NDSP 431 is output tothe outside via Oram1 (see FIG. 6). Because the MDSP is not used at allin the output-side processing, a gate may be provided on a line overwhich the operation clocks are supplied to the MDSP, and the output-sideMLSI may close the gate so as to prevent the operation clocks from beingsupplied to the MDSP; in this way, it is possible to reduce powerconsumption by an amount corresponding to the prevention of theoperation clock supply. As a variation or modification, the result ofthe output-side adjustment processing by the NDSP 431 may be passed viaMram1 to the MDSP 432 to allow the MDSP 432 to perform the mixingprocessing on the result of the output-side adjustment processing; inthis case, arrangements may be made to allow the result of theoutput-side adjustment processing to be mixed with thecascade-transferred signals with the gate 815 opened.

The following paragraphs describe details of the mixing processingperformed by the MDSP 432 of FIG. 8. FIG. 9 is a time chart explanatoryof the mixing processing performed by the MDSP 432 in the individualmodes. Reference numeral 901 in (a) of FIG. 9 shows a manner in whichword clocks WC are sequentially generated in accordance with the passageof time, one word clock WC per sampling period, as indicated at 903-1,903-2, . . . Reference numeral 902 shows in enlarged scale one samplingperiod between the word clocks 903-1 and 903-2.

910 in (b) of FIG. 9 is a block showing an operational flow of themixing processing performed in one sampling period by the MDSP 432 in“mode 1”, which corresponds to the mixing processing 522 explained abovein relation to FIG. 5. The mixing processing of block 910 is started apredetermined time “front jitter margin 531+difference margin 532” afterthe timing 903-1 of the corresponding word clock WC, and, aftercompletion of the mixing processing, a rear jitter margin 533 is securedtill the next word clock WC 903-2. 914 indicates a period of eachoperation clock in which the MDSP 432 performs an operation of one step.“Operation Clock within MLSI” row 911 in (b) of FIG. 9 indicates asequence of the numbers (0-3,072) of the 3,072 steps performed by theMDSP 432. “Input Channel” row 912 indicates input channels of whichsignals are to be read out from the I/O RAM 811. “Bus” row 913 showsmixing buses via which the mixing processing is to be performed.

The following paragraphs explain operations of the individual stepssequentially performed in “mode 1” with reference to (b) of FIG. 9.

(1) First, the operation of “step 0” is explained. In the MDSP 432 ofFIG. 8, an address corresponding to “step 0” is read out from the readaddress memory 803, and data stored at the address of the I/O RAM 811(Mram) (this data corresponds to “i1” indicated immediately below “step0” in FIG. 9 and will hereinafter be referred to as “data of chi1”) isinput to the multiplier 812. Result of the input channel adjustmentprocessing by the NDSP 431 or signal (sample data) input via the inputsection (IN) 435 has been written at the above-mentioned address of theMram at least by the preceding step. Further, coefficient datacorresponding to “step 0” is input from the supply section 801 to themultiplier 812. The multiplier 812 multiplies the data read out from theMram and the input coefficient data, and the result of themultiplication is input to the adder 814. At “step 0”, a control signalis given such that the selector 813 selectively outputs “0”. Thus, theadder 814 adds the value “0” and the abovementioned multiplicationresult, and the result of the addition is stored into the not-shownaccumulator for use at the next step as noted above in relation to FIG.8.

(2) The operation of step 1 is described below. In the MDSP 432, anaddress corresponding to “step 1” is read out from the read addressmemory 803, and data stored at the address of the Mram (i.e., “data ofchi2” indicated immediately beneath “step 1” in the row 912) is input tothe multiplier 812. Further, coefficient data corresponding to “step 1”is input from the supply section 801 to the multiplier 812. Themultiplier 812 multiplies the data read out from the Mram and the inputcoefficient data, and the result of the multiplication is input to theadder 814. At “step 1”, a control signal is given such that the selector813 selectively outputs the addition result, stored in the not-shownaccumulator at preceding “step 0”. Thus, the adder 814 adds thepreceding addition result and the abovementioned multiplication result,and the result of the addition by the adder 84 is stored into thenot-shown accumulator for use at the following step. Operations similarto the aforementioned are performed at “step 2” through “step 31”.Assuming that the currently-set mode is “mode 1”, the NDSP 431 in theMLSI performs the adjustment processing for 32 channels. Thus, thesignals of all of the 32 channels, generated within the MLSI, can bemixed together by writing the signals of the 32 channels into the Mram,then reading out the thus-written signals from the Mram as the data of“chi1-chi32” and performing the product-sum calculations to multiply theread-out signals by the corresponding coefficients and accumulating theresults of the multiplication. The result of the mixing is then outputfrom the adder 814 at “step 31”.

(3) At “step 31” depicted at 915-1 in (b) of FIG. 9, the followingprocess is performed following the process of (2) above. At the timingthe mixing result of all of the 32 channels, generated within the MLSI,is output from the adder 814, signals cascade-transferred from thepreceding-stage MLSDI are received from the cascade input section (CIN)433 via the gate 815, and the addition result output from the adder 814is added with the cascade signal. In the case of the MLSI I22-1 shown inFIG. 1A, to which no cascade signal is input (i.e., whose cascade inputterminal is connected with nothing), it is assumed that a value “0” isalways input thereto, so that the adder 814 adds the mixing resultoutput therefrom with the value “0”. The result of the addition by theadder 816 is written into a predetermined address of the I/O RAM 811.What is cascade-transferred from the preceding-stage MLSI at the timing915-1 is a signal of “mixing bus 0” (MIX1). Further, because therespective coefficient data by which the data of “chi1”-“chi32” aremultiplied can be set as desired, data of “chi*” that is not to be mixedwith the signal of “mixing bus 0” (i.e., that is not to be mixed to“mixing bus 0”) can be prevented from being mixed to “mixing bus 0”, bysetting the corresponding coefficient data in the coefficient memory at“0”. Namely, in short, the addition by the above-mentioned adder 816means adding a mix of the signals to be mixed to “mixing bus 0” fromamong the signals of all of the channels generated in the MLSI (i.e.,output from the adder 814) and the signal of “mixing bus 0” input fromthe preceding-stage MLSI (i.e., output from the gate 815). As explainedabove in relation to FIG. 6, the addition result of the adder 816(mixing result of “mixing bus 0”) is mechanically written intoaddresses, corresponding to “mixing bus 0”, of Nram2, Oram2 and Cram1.

(4) At “step 32” through “step 63”, operations similar to those of “step0” through “step 31” are performed, except that the mixing is performedhere for “mixing bus 1” (MIX2) instead of “mixing bus 0”. Then,operations of “step 3040”-“step 3071” are performed to sequentiallyperform the mixing up to the mixing for “mixing bus 95” (R of stereo B)in a manner similar to the aforementioned.

In the above-described manner, it is ensured that desired ones ofsignals of the 32 channels, generated by the MLSI, can be mixed withsignals of desired ones of the 96 mixing buses (i.e., can be mixed todesired ones of the 96 mixing buses). As seen from the foregoingdescription, control is performed in “mode 1” such that the addition bythe adder 816 and writing, into Nram2, Oram2 and Cram1, of the result ofthe addition (mixing) by the adder 816 is executed at the timing of“step 31”, “step 63”, . . . , “step 3,030” and “3,071” (i.e.,915-1-915-96 in (b) of FIG. 9) so that the selector 813 selectivelyoutputs the value “0” at the timing of “step 0”, “step 32”, “step 64”, .. . , “step 3,040”. These timing is detected by the mixing-result outputtiming signal generation section 807, so that predetermined controlsignals are supplied to the various sections of the MDSP 432 (as will belater detailed in relation to FIGS. 10A and 10B).

Whereas (b) of FIG. 9 shows the case where the currently-set mode is“mode 1”, operations similar to the aforementioned are performed in theother modes. In the case of “mode 2” shown in (c) of FIG. 9, where thenumbers of input channels and mixing buses are “64” and “48”,respectively, the mixing is performed for the group of 64 channels, andthe mixing result is mixed with signals of the 48 mixing buses at steps63, 127, . . . , 3,071 (925-1, . . . , 925-48 in (c) of FIG. 9). In thecase of “mode 3” shown in (d) of FIG. 9, where the numbers of inputchannels and mixing buses are “24” and “128”, respectively, the mixingis performed for the group of 24 channels, and the mixing result ismixed with signals of the 128 mixing buses at steps 23, 47, . . . , 3071(935-1, . . . , 935-128 in (d) of FIG. 9). Further, in the case of “mode4” shown in (d) of FIG. 9, where the numbers of input channels andmixing buses are “48” and “64”, respectively, the mixing is performedfor the group of 48 channels, and the mixing result is mixed withsignals of the 48 mixing buses at steps 47, 95, . . . , 3,071 (945-1, .. . , 945-64 in (e) of FIG. 9).

Whereas, in each of the modes in the illustrated example of FIG. 9,“chi1”, “chi2”, . . . are indicated as the input channels to be mixedwith the signals of the individual mixing buses, even the same “chi1”,for example, does not necessarily use the same signal. This is because,a read address of the Mram can be set in the address memory 803 for eachof the 3,072 steps as noted above in relation to FIG. 8. Thus, a desiredsignal can be input for mixing into (i.e., mixing with signals of) themixing buses; for example, a signal of “chi1” to be mixed to “MIX1” at“step 0” in “mode 1” may be taken out at the pre-fader position of FIG.3 (i.e., output of the compressor (Comp) 303), a signal of “chi1” to bemixed to “MIX2” at step “step 32” may be taken out at the post-faderposition of FIG. 3 (i.e., output of the channel-ON switch (CH_ON) 305,and so on.

As set forth above, the MDSP 432 of the MLSI is a DSP capable ofperforming 3,072 product-sum calculations (i.e., product-sum calculationprocessing of 3,072 steps) (each consisting of one multiplication andone addition) within each sampling period, and such 3,072 product-sumcalculations are used in accordance with any one of combinations (basedon “number of channels×number of mixing buses=3,072”) which correspondsto the currently-set mode. Generally, it is only necessary that the MDSP432 be constructed as shown in FIG. 8 and in the manner as stated at(1)-(3) below.

(1) The MDSP 432 is a DSP constructed to perform H (H=J×K) (“J” and “K”are each an integral number greater than “1”) product-sum calculationswithin each sampling period, and let it be assumed that a plurality ofcombinations, such as (J₁, K₁) and (J₂, K₂), are possible with respectto the fixed value H. These combinations are allocated to “mode 1”,“mode 2”, . . . , and, in “mode m” (m=1, 2, . . . ), the number ofchannels is J_(m) while the number of mixing buses is K_(m). In theillustrated example of (b) of FIG. 1, for example, H=3,072, and J₁=32and K₁=96 in “mode 1”, J₂=64 and K₂=48 in “mode 2”, J₃=24 and K₃=128 in“mode 3”, and J₄=48 and K₄=64 in “mode 4”.

(2) Then, the control signal generation section 806 generates controlsignals corresponding to the set mode.

Thus, within each sampling period, the selector 813 is caused toselectively output “0” at each of steps h (=0, J_(m), 2 J_(m), . . . ,(K_(m)−1)×J_(m)), and the multiplier 812 and adder 814 performarithmetic operations of “data[h]×coefficient[h]+‘0’—accumulator”.

At each of the other steps h, the selector 813 is caused to selectivelyoutput the output of the adder 814 produced at the preceding step, i.e.value of the not-shown accumulator, and the multiplier 812 and adder 814perform arithmetic operations of“data[h]×coefficient[h]+accumulator→accumulator”. Here, “data[h]” isdata read out from the Mram with a read address, corresponding to “steph”, stored in the read address memory 803, “coefficient[h]” is acoefficient value, corresponding to “step h”, supplied from thecoefficient memory 802, and “h” indicates a step number that is anintegral number in the range of “0” to “H−1”.

(3) Further, at each of steps h (=J_(m)−1, 2J_(m)−1, . . . ,K_(m)×J_(m)−1), the adder 816 performs arithmetic operations of“accumulator+cascade signal→Nram2, Oram2 and Cram1”. These areoperations in which a signal cascade-transferred from thepreceding-stage MLSI is input via the cascade input section (CIN) 433and gate 815 and then the addition result output from the adder 814 andthe cascade-transferred signal are added together via the adder 816.Here, the mixing result of “mixing bus 0”, mixing result of “mixing bus1”, . . . , and mixing result of “mixing bus K_(m)−1” are written atsteps J_(m)−1, 2J_(m)−1, . . . , and K_(m)×J_(m)−1, respectively, intolocations, corresponding to the mixing buses, of Nram2, Oram2 and Cram1.

In the aforementioned manner, each of the MDSPs can be constructed in ageneralized form. From the viewpoint of the construction of the DSP, itis reasonable to set “J” and “K” at values containing powers of two. Forexample, it is preferable to set “J” at a value “a×2^(s)” and “K” at avalue “b×2^(t)” and allocate “J” and “K” to a plurality of modes withvarious different combinations of values of “s” and “t”.

FIG. 10A shows a detailed construction of the mixing-result outputtiming signal generation section 807 shown in FIG. 8, which includes adetection section 1001, 6-bit counter 1002 and timing signal generationsection 1003. The 6-bit counter 1002 is reset to “0” at “step 0” andthen counts up every operation clock, i.e. per step. The detectionsection 1001 detects a time point when the 6-bit counter 1002 haspresented any one of 6-bit patterns, shown in FIG. 10B, corresponding tothe currently-set mode. Namely, in “mode 1”, the detection section 1001detects respective timing of “step 31”, “step 63”, . . . , “step 3039”and “step 3071” shown in (b) of FIG. 9; in “mode 2”, the detectionsection 1001 detects respective timing of “step 63”, “step 127”, . . . ,“step 3071” shown in (c) of FIG. 9; in “mode 3”, the detection section1001 detects respective timing of “step 23”, “step 47”, . . . , “step3071” shown in (d) of FIG. 9; and, in “mode 4”, the detection section1001 detects respective timing of “step 47”, “step 95”, . . . , “step3071” shown in (e) of FIG. 9. At each of the detected timing, controlsignals are generated such that the addition by the adder 816 andwriting, into Nram2, Oram2 and Cram1, of the result of the addition iseffected. Because the result of the addition is written into locations,corresponding to the mixing bus, of Nram2, Oram2 and Cram1 as explainedabove in relation to FIG. 6, the mixing-result output timing signalgeneration section 807 includes a counter (not shown) for providing acount indicating at which position in one sampling period the currentwrite timing has been generated (i.e., which number write timing in thesampling period the current write timing is), and it generates a controlsignal such that the addition result is written into locationscorresponding to the count value of the counter. The detection section1001 outputs a reset signal, at a step immediately following the timepoint when any one of the patterns shown in FIG. 10B has been detected(e.g., at the time point of each of “step 32”, “step 64”, . . . , “step3040”), to reset the 6-bit counter 1002 to “0”. Further, at that timepoint, the timing signal generation section 1003 generates a controlsignal to control the selector 813 to selectively output the value “0”.

FIG. 11 is a conceptual diagram showing flows of signals when theplurality of MLSIs, interconnected as shown in FIG. 1A, perform theprocessing explained above in relation to FIGS. 7-10B. Thick-line blockindicated at “MLSI I1” represents the arithmetic processing performed by“MLSI I1” of FIG. 1A. Similarly, thick-line blocks indicated at “MLSII2”-“MLSI In” represent the arithmetic processing performed by “MLSII2”-“MLSI In”. In “MLSI I1”, signals of j (integral number) inputchannels (i.e., signals received via the input section 111-1) are inputvia lines 1102-1-1102-j. These lines 1102-1-1102-j represent passing ofsignals, input via the input section (IN) 435, to the NDSP 431 via Nram3(see FIGS. 4 and 6). When the currently-set is “mode 1”, for example,j=32 because the number of input channels is “32” in “mode 1”. “EQ/Comp”blocks 1103-1-1103-j each represent the adjustment processing for one ofthe input channels performed by the NDSP 431 of “MLSI I1” (see FIG. 3).Outputs from the adjustment processing of the individual input channelsare supplied, via lines 1104-1-1104-j, to a dotted-line block 1105-1.This block 1105-1 represents the mixing processing performed by the MDSP432 of “MLSI I1”. Lines 1104-1-1104-j represent passing of signals fromthe NDSP 431 to the MDSP 432 via Mram1 (see FIGS. 4 and 6).

Lines 1106-1-1106-k, vertically extending across the mixing processing1105-1-1105-n, represent k (integral number) mixing buses. When “mode 1”is set, for example, k=96 because the number of mixing channels is “96”in “mode 1”. Assuming that the lines 1106-1-1106-k represent “mixing bus0”, “mixing bus 1”, . . . , “mixing bus k−1”, respectively, intersectionpoints between the line 1106-1 corresponding to “mixing bus 0” and thelines 1104-1-1104-j corresponding to the individual input channels, forexample, represent mixing the signals of the individual channels within“MLSI I1” to “mixing bus 0”. Description similar to the aforementionedapply to “MLSI I2”-“MLSI In”. However, as stated above, the actualproduct-sum calculations performed in the instant embodiment comprise:first mixing signals of the individual input channels within each of theMLSIs; then mixing the result of the mixing within the MLSI with acascade-transferred signal of the mixing bus; and thencascade-transferring the result of the mixing by the mixing bus to thenext-stage MLSI. Signal of each of the mixing buses cascade-transferredfrom the last-stage, input-side MLSI (i.e., “MLSI In”) is supplied tothe output-side MLSIs; only “MLSI O1” is shown in FIG. 11. “EQ/C” blocks1122 represent the output-side adjustment processing performed in “MLSIO1”. 1120 and 1121 represents signals delivered to the output sections112-1-112-3. In the MLSIs, the combination of values of “j” and “k” canbe changed as the set mode is changed.

FIG. 12 is a time chart of the cascade transfer. (a) of FIG. 12 showstiming 1201-1-1201-5 of the word clocks WC. (b) of FIG. 12 showsbehavior of the first MLSI (hereinafter referred to as “MLSI1”) in firstand second sampling periods, and (c) of FIG. 12 shows behavior of thesecond MLSI (hereinafter referred to as “MLSI2”). Let it be assumed herethat the cascade-transfer output terminals of “MLSI1” are connected tothe cascade-transfer input terminals of “MLSI2”. The followingparagraphs describe an operational sequence of the cascade transfer from“MLSI1” to “MLSI2”, assuming that “mode 1” is currently set and “MLSI1”is a leading MLSI in the cascade transfer flow.

In (b) and (c) of FIG. 12, “Latch-to-FIFO” sections 1202-1, 1202-2 and1205-1, 1205-2 are where each of the MLSIs performs, in each samplingperiod, receiving-side processing for receiving signalscascade-transferred from the preceding-stage MLSI and sequentiallylatching the received signals into the FIFO within the cascade inputsection (CIN) 433. “Mixing Processing” sections 1203-1, 1203-2 and1206-1, 1206-2 are where signals having been subjected to the adjustmentprocessing within each of the MLSIs are mixed to (i.e., mixed withsignals) the individual mixing buses. “Cram1 (write)” indicates a mannerin which mixing results are sequentially stored into Cram1 shown inFIGS. 4 and 6, instead of indicating a time wise flow. MIX1, MIX2, ofCram1 indicate regions for storing the mixing results of “mixing bus 0”,“mixing bus 1”, “Cascade Transfer” sections 1204-1, 1204-2 and 1207-1,1207-2 are where signals are cascade transferred from the MLSI to thesucceeding-stage MLSI (transmitting-end processing).

In the mixing processing section 1203-1, “MLSI1” performs the mixingprocessing of the block 910 in “mode 1”. Then, “MLSI1” sequentiallywrites the mixing results of “mixing bus 0”-“mixing 95” into Cram1 (andNram2 and Oram2) at timing 915-1-915-96. More specifically, in (b) ofFIG. 12, a section 1211 corresponds to processing sections of “step0”-“step 31” shown in (b) of FIG. 9, and a section 1212 corresponds toprocessing sections of “step 32”-“step 63” shown in (b) of FIG. 9; theother sections 1213, . . . correspond to processing sections of theother steps. Thus, end timing of the section 1211 corresponds to thetiming 915-1 in (b) of FIG. 9 and end timing of the section 1212corresponds to the timing 915-2 in (b) of FIG. 9; therefore, the mixingresult of “mixing bus 0” (i.e., result of signals being mixed to “mixingbus 0” from among the signals of all of the channels generated by“MLSI1”) is written into Cram1 (MIX1) at timing A, the mixing result of“mixing bus 1” is written into Cram1 (MIX2) at timing B, and then in asimilar manner to the aforementioned, the mixing results of “mixing bus2” through “mixing bus 95” are written into Cram1 in the section 1203-1.As explained above in relation to FIG. 9, the mixing results to bewritten into Cram1 in each of the MLSIs are the results of adding thesignals, cascade-transferred from the preceding-stage MLSI, with themixing result of the signals of the individual channels having beensubjected to the adjustment processing in the MLSI. However, becausethere is no MSLI that precedes “MLSI1”, no cascade signal is added tothe mixing result of the signals having been subjected to the adjustmentprocessing by “MLSI1”. Therefore, what is written into Cram1 in themixing processing in the section 1203-1 is just the mixing result of thesignals of the individual channels having been subjected to theadjustment processing by “MLSI1”. The mixing processing performed in andafter the mixing processing section 1203-2 of the second sampling periodis similar to the aforementioned mixing processing.

In the cascade transfer section 1204-2 of the second sampling period,the individual data of “mixing bus 0”-“mixing bus 95”, written intoCram1 in the above-mentioned mixing processing section 1203-1, arecascade-transferred to “MLSI2”. First, transfer, from Cram1, of the dataof “mixing bus 0” (MIX1) is started at timing (1), carried out in thesection 1221 and ended at timing (2).

Then, transfer of the data of “mixing bus 1” (MIX2) is started at timing(2), carried out in the section 1222 and ended at timing (4). In asimilar manner to the aforementioned, transfer, from Cram1, of the dataof “mixing bus 3” through “mixing bus 95” is sequentially carried out.Note that, in “model”, transfer of one data (32 bits) is carried out inresponse to four transfer clocks (32 operation clocks): the transferclock will be later described with reference to FIG. 13.

Mixing processing is performed in the mixing processing section 1203-2of the second sampling period, in a similar manner to the mixingprocessing performed in the mixing processing section 1203-1. Namely,the mixing result of “mixing bus 0” is written into Cram1 (MIX1) at endtiming (3) of the section 1213, the mixing result of “mixing bus 1” iswritten into Cram1 (MIX2) at end timing (5) of the section 1214, andthen in a similar manner to the aforementioned, the mixing results of“mixing bus 2” through “mixing bus 95” are written into Cram1.

Timing (1)-timing (5) indicates timewise order. Namely, transfer, fromCram1, of the mixing result of “mixing bus 0” (MIX1) is started attiming (1), and after termination of the transfer at timing (2), themixing result of “mixing bus z” (MIX2) is written into Cram1 at timing(3) a little later than timing (2). Thus, in the regions of Cram1storing the mixing results of the individual mixing buses, the nextmixing result is written after the cascade transfer of the previousdata, so that there occurs no conflict between the data in Cram1. Thisis because the cascade transfer processing is effected earlier than themixing processing by the difference margin, and a receiving-end LMSItemporarily latches the received data into the FIFO register and thenuses the data by reading out the latched data at necessary timing.Because the Cram in the instant embodiment has the dual structurecomprising the front-side storage area and back-side storage area asexplained above in relation to FIG. 6, there would occur no problem evenif the writing and reading is performed simultaneously.

The data each of the mixing buses cascade-transferred in the section1204-2 is received and latched through the receiving-end processing inthe section 1205-5 by “MLSI2” at the succeeding stage. Namely, first,the reception and latching, into the FIFO of the cascade input section(CIN) 433, of the data of “mixing bus 0” (MIX1) cascade-transferred from“MLSI1” is started at timing (11). The reception and latching is carriedout in a section 1231 (corresponding to the section 1221 of MLSI1), andthe latching is terminated at timing (12); by that time, the data of“mixing bus 0” has been written in the FIFO register. Likewise, the dataof “mixing bus 1” are received and latched in section 1232(corresponding to the section 1222 of MLSI1). In a similar manner to theaforementioned, the signals of the other mixing buses,cascade-transferred from “MLSI1”, are received and latched.

Meanwhile, mixing processing is performed in the sections 1206-1 and1206-2 by “MLSI2” in a similar manner to that in the sections 1203-1 and1203-2 by “MLSI1”. To explain more specifically the mixing processing inthe section 1206-2, for example, a section 1241 corresponds toprocessing sections of “step 0”-“step 31” in (b) of FIG. 9, end timing(13) of the section 1241 corresponds to the timing 915-1 in (b) of FIG.9, a section 1242 corresponds to processing sections of “step 32”-“step63” in (b) of FIG. 9, end timing (15) of the section 1242 corresponds tothe timing 915-2 in (b) of FIG. 9, and so on. Thus, a mixing result ofthe signals of the individual channels having been subjected to theadjustment processing by “MLSI2” (i.e., signal to be mixed to (i.e.,mixed with signals of) “mixing bus 0”) is acquired in the section 1241,and the data of “mixing bus 0”, already latched after reception viacascade transfer, is added to the acquired mixing result at end timing(13), and the result of the addition is written into Cram1 as data of“mixing bus 0” (MIX1). Further, a mixing result of the signals of theindividual channels having been subjected to the adjustment processingby “MLSI2” (i.e., signal to be mixed to “mixing bus 1”) is acquired inthe section 1242, and data of “mixing bus 1”, already latched afterreception via cascade transfer, is added to the acquired mixing resultat end timing (15), and the result of the addition is written into Cram1as data of “mixing bus 1” (MIX2). Then, in a similar manner to theaforementioned, signals having been subjected to the adjustmentprocessing by “MLSI2” are written into Cram1 after being reflected in“mixing bus 2” through “mixing bus 95”. The data of “mixing bus 0”through “mixing bus 95”, having been written into Cram1 in each samplingperiod in the aforementioned manner, are cascade-transferred to thesucceeding-stage MLSI by the transmitting-end processing (cascadetransfer sections 1207-1, 1207-2, etc.) in the next sampling period.During that time, there would occur no conflict between the data writingand reading, as noted above. Subsequent cascade transfer is performed ina similar manner to the aforementioned.

As understood from the foregoing, results of the mixing processingperformed in a given sampling period by a given MLSI in the instantembodiment are cascade-transferred to the succeeding-stage MLSI in thenext sampling period; thus, the time delay caused by the cascadetransfer has a length equal to just one sampling period. Namely, ifsamples simultaneously input from the individual input sections111-1-111-n to individual “MLSI I1”-“MLSI In” in the illustrated exampleof FIG. 1A are considered, and assuming that the timing at which signalsare reflected in the mixing buses in the last-stage input-side MLSI(MLSI In) is considered as reference timing, the samples input from theinput section 111-n−1 are reflected in the mixing buses after beingdelayed by one sampling period, the samples input from the input section111-n−2 are reflected in the mixing buses after being delayed by twosampling period, and so on; the samples input from the input section111-1 are reflected in the mixing buses after being delayed by (n−1)sampling period. With the prior art technique, on the other hand, in thecase where two DSPs are interconnected, data transfer between the DSPswould take at least one sampling period and processing in thereceiving-end DSP would take one sampling period; thus, a time delay ofa total length equal to two sampling periods would occur between theinterconnected DSPs. However, the MLSIs in the instant embodiment caneach reduce the time delay to a length equal to just one sampling periodand thus are suited for application to business-use equipment whoserequested specifications are very strict with respect to the sampledisplacements.

Because the order in which the MLSIs are cascade-connected as shown inFIG. 1A is known in advance, it is possible to eliminate sampledisplacements when the samples are reflected in the mixing buses, bycontrolling the input of the samples, introduced simultaneously to theindividual input sections 111-1-111-n, such that the input section 111-1inputs the samples to “MLSI I1” with no time delay, the input section111-2 inputs the samples to “MLSI I2” with a time delay corresponding toone sampling period, . . . , and the input section 111-n inputs thesamples to “MLSI In” with a time delay corresponding to (n−1) samplingperiod.

FIGS. 13A-13B show details of bit data transferred in the cascadetransfer between the MLSIs. As explained earlier in relation to FIGS. 1Aand 1B, the number of mixing buses to be used for mixing per samplingperiod (i.e., number of data to be transferred via the mixing buses persampling period) differs among the modes. Further, although the internalcomponents in each of the MLSIs operate in accordance with the operationclocks, the data transfer between the MLSIs has to be executed inaccordance with clocks slower than the operation clocks, in order tosecure sufficient operational reliability. Thus, in the instantembodiment, the number of transfer lines and the frequency of the clocksto be used for the transfer are changed in accordance with the mode sothat necessary data can be transferred in each sampling period in eachof the modes.

FIG. 13A shows the transferred bit data in “mode 1”. In “mode 1”, it isnecessary to transfer all of data of “mixing bus 0”-“mixing bus 95”(32×96 bits in total because each data is of 32 bits) in each samplingperiod. For that purpose, the instant embodiment uses eight (serial)transfer lines between the MLSIs to transfer data of 32 bits every fourtransfer clocks. The transfer clocks are generated by dividing thefrequency of the operation clocks by eight. Thus, in each samplingperiod, it is possible to effect data transfer corresponding to 3,072operation clocks. i.e. 384 transfer clocks; because one data can betransferred every four transfer clocks (32 operation clocks), 96 (384/4)data can be transferred in each sampling period in this mode; these 96data correspond to data of “mixing bus 0”-“mixing bus 95”. Sectionlabeled “mixing bus 0” indicates a manner in which one data (of 32bits), corresponding to a given sampling period, of a signal of “mixingbus 0” is cascade-transferred using the eight transfer lines and inaccordance with four transfer clocks; cascade transfer of one data iseffected in each of “mixing bus 1” through “mixing bus 95” in the samemanner as in “mixing bus 0”. The section “mixing bus 0” in FIG. 13Acorresponds to “operation clock 0”-“operation clock 31” in (b) of FIG.9, section “mixing bus 1” in FIG. 13A corresponds to “operation clock32”-“operation clock 63” in (b) of FIG. 9, . . . , and section of“mixing bus 95” in FIG. 13A corresponds to “operation clock3,040”-“operation clock 3,071” in (b) of FIG. 9. However, the cascadetransfer processing is effected earlier than the mixing processing bythe difference margin, as set forth above in relation to FIG. 5, etc.

By effecting the cascade transfer in “mode 1” in the aforementionedmanner, it is possible to ensure the operation timing explained above inrelation to FIGS. 9 and 12. In (b) of FIG. 9, for example, reception andlatching of data of “mixing bus 0” has already been completed at thetiming 915-1, reception and latching of data of “mixing bus 1” hasalready been completed at the timing 915-2, and so on. In this way, itcan be ensured that reception and latching, from the preceding-stageMLSI, of the data of the individual mixing buses in the MLSI in questionhas been completed by the time point when data to be added or mixed tothe individual mixing buses is generated.

FIG. 13B shows the transferred bit data in “mode 2”. In “mode 2”, it isnecessary to transfer all of data of “mixing bus 0”-“mixing bus 47” ineach sampling period. For that purpose, the instant embodiment uses fourtransfer lines between the MLSIs to transfer data of 32 bits every eighttransfer clocks. The transfer clocks are generated by dividing thefrequency of the operation clocks by eight. Thus, in each samplingperiod, it is possible to effect data transfer corresponding to 3,072operation clocks. i.e. 384 transfer clocks; because one data can betransferred every eight transfer clocks, 48 (384/8) data can betransferred in each sampling period in this mode; these 48 datacorrespond to data of “mixing bus 0”-“mixing bus 47”.

FIG. 13C shows the transferred bit data in “mode 3”. In “mode 3”, it isnecessary to transfer all of data of “mixing bus 0”-“mixing bus 127” ineach sampling period. For that purpose, the instant embodiment useseight transfer lines between the MLSIs to transfer data of 32 bits inaccordance with four transfer clocks. The transfer clocks are generatedby dividing the frequency of the operation clocks by six. Thus, in eachsampling period, it is possible to effect data transfer corresponding to3,072 operation clocks. i.e. 512 transfer clocks; because one data canbe transferred every four transfer clocks, 128 (512/4) data can betransferred in each sampling period in this mode; these 128 datacorrespond to data of “mixing bus 0”-“mixing bus 127”.

FIG. 13D shows the transferred bit data in “mode 4”. In “mode 4”, it isnecessary to transfer all of data of “mixing bus 0”-“mixing bus 63” ineach sampling period. For that purpose, the instant embodiment uses fourtransfer lines between the MLSIs to transfer data of 32 bits inaccordance with eight transfer clocks. The transfer clocks are generatedby dividing the frequency of the operation clocks by six. Thus, in eachsampling period, it is possible to effect data transfer corresponding to3,072 operation clocks. i.e. 512 transfer clocks; because one data canbe transferred every eight transfer clocks, 64 (512/8) data can betransferred in each sampling period in this mode; these 64 datacorrespond to data of “mixing bus 0”-“mixing bus 63”.

As noted above, the instant embodiment is constructed to change thenumber of transfer lines to be used for the cascade transfer inaccordance with the set mode. This means that the instant embodiment canchange the functions of predetermined pins in accordance with the setmode; the pins not used for the cascade transfer are usable for theordinary function.

Further, for the serial transfer over each of the cascade transferlines, the MLSI at the data-receiving end supplies the transfer clocks,while the MLSI at the data-receiving end receives data in synchronismwith the transfer clocks. Thus, even where the MLSIs are operating inaccordance with their respective operation clocks, the cascade transferbetween the MLSIs can be carried out appropriately with no problem.

The mixer according to the instant embodiment shown in FIG. 1A includesa user interface via which any one of the modes shown in FIG. 1B can bedesignated from a not-shown personal computer (PC) connected to themixer via the communication I/O interface 147 and functionalconstructions of the mixer and channels shown in FIGS. 2 and 3 can beset from the not-shown personal computer. More specifically, a mixerconstruction editing program can be executed on the personal computer todesignate a desired one of the modes and create/edit the constructionsof FIGS. 2 and 3 on a display screen. The thus-created (edited) mixerconstruction and channel construction are each converted into a dataformat interpretable by the mixer of FIG. 1A after compilation by thepersonal computer, and the thus-converted data are transferred to themixer. The CPU 141 of the mixer of the invention analyzes thetransferred data and sets control registers of the individual MLSIs suchthat the designated functional constructions can be implemented. In thisway, the desired mixer construction can be implemented. In operation ofthe mixer, a current memory is secured within the RAM 143, and controldata for controlling current signal processing of the mixer are storedinto the current memory; for example, the control data are valuesindicative of operational states of the operator unit 146. As any one ofthe operators of the operator unit 146 is operated, the control data,corresponding to the operated operator, stored in the current memory ischanged in accordance with the operation of the operator. Such a changein the control data is reflected in the control registers of the MLSIs.For example, (1) when a fader corresponding to the volume control (Vol)304 of FIG. 3 is operated, the value of the corresponding coefficientdata stored in the coefficient memory 702 is changed, (2) when a switchcorresponding to the channel-ON switch (CH_ON) 305 of FIG. 3 is turnedoff, the corresponding coefficient data stored in the coefficient memory702 is changed to “0”, (3) when a switch corresponding to the pre/postswitch (PP) 308 of FIG. 3 is operated, the corresponding address storedin the address memory 803 is changed, and so on.

In the above-described embodiment, each of the MLSIs is constructed tooperate in accordance with the clocks generated by a separate orindependent operation clock generator through operation of a quartsoscillator. Alternatively, some of the MLSIs, adjoining each other, maybe grouped so that all of the MLSIs of that group may be caused tooperate in accordance with same clocks, because causing such adjoiningMLSIs to operate in accordance with same clocks is not so difficult.

With the conventionally-known transfer techniques (using serial buses,audio buses, etc.), it used to take two sampling periods for a giveninput-side integrated circuit to receive audio signals from apreceding-stage input-side integrated circuit, perform addition permixing bus and transmit results of the addition to a succeeding-stageinput-side integrated circuit. However, the above-described embodiment,where, for every two cascade-connected input-side MLSIs, the timing ofthe addition processing in the mixing buses in the receiving-end MLSI iscontrolled to agree with the timing of the cascade-transferred signals,can reduce the time delay per MLSI to one sampling period, i.e. reducethe time delay per MLS by half as compared to the conventionally-knowntransfer techniques. By improving the aforementioned scheme of theinstant embodiment, the time delay per MLSI can be reduced below onesampling period. More specifically, in each of the MLSIs, arrangementsmay be made such that the mixing processing is started a firstdifference margin after the start of the cascade reception process andthen the cascade transmission process is started a second differencemargin after the start of the mixing processing. Further, the operationtiming of the cascade-connected MLSIs is adjusted so that the operationtiming of the cascade transmission process of the preceding-stage MLSIagrees with the timing of the cascade reception process of thesucceeding-stage MLSI. Here, the first difference margin is the same asthe difference margin mentioned earlier, while the second differencemargin is of a time length within which the processing in the individualmixing buses can be completed. In this case, the time delay per MLSI canbe reduced to about the sum of the first and second difference margins.

Whereas the preferred embodiment has been described above in relation tothe case where the input-side signal processing integrated circuits andthe output-side signal processing integrated circuits are of the sametype, they may be of different types.

1. An integrated circuit for processing digital audio signals everysampling period, comprising: a plurality of blocks including: an inputblock that supplies audio signals inputted from outside; an output blockthat outputs supplied audio signal to outside; and a signal processingblock that performs signal processing on audio signals supplied theretoto thereby supply the processed audio signal; and a plurality ofcommunication memories corresponding to a plurality of transfer paths,from a sender in said blocks to a receiver in said blocks, each of saidcommunication memories including a front-side memory and a back-sidememory, and roles of the front-side memory and the back-side memoryalternate each other every sampling period, wherein each communicationmemory of each transfer path is dedicated to the transfer path such thata block as a sender of a transfer path can write audio signals into thefront-side memory of the communication memory corresponding to thetransfer path without being affected by the other block, and a block asa receiver of a transfer path can read audio signals from the back-sidememory of the communication memory of the transfer path without beingaffected by the other block.
 2. An integrated circuit as claimed inclaim 1 which includes a plurality of the signal processing blocks, andsaid plurality of transfer paths include a transfer path between thesignal processing blocks.